公开(公告)号：WO2020198223A1

公开(公告)日：2020-10-01

申请号：PCT/US2020/024458

申请日：2020-03-24

Applicant: QUALCOMM INCORPORATED

Inventor： DU, Yun ,  GRUBER, Andrew Evan ,  YU, Chun ,  ZHANG, Chihong ,  SHANG, Hongjiang ,  YING, Zilin ,  WEI, Fei

IPC: G06T15/00 ,  G06T15/04 ,  G06T1/60

Abstract: Example techniques are described for generating graphics content by obtaining texture operation instructions corresponding to a texture operation, in response to determining at least one of insufficient general purpose register space is available for the texture operation or insufficient wave slots are available for the texture operation, generating an indication that the texture operation corresponds to a deferred wave, executing the texture operation, sending, to a texture processor, initial texture sample instructions corresponding to the texture operation that was executed, and receiving texture mapped data corresponding to the initial texture sample instructions.

公开(公告)号：WO2018022187A1

公开(公告)日：2018-02-01

申请号：PCT/US2017/035038

申请日：2017-05-30

Applicant: QUALCOMM INCORPORATED

Inventor： KAZAKOV, Maxim ,  GRUBER, Andrew Evan

IPC: G06T15/00 ,  G06T1/20

CPC classification number: G06T1/20 ,  G06T15/005

Abstract: This disclosure describes examples of using two vertex shaders each one during different graphics processing passes in a binning architecture for graphics processing. A first vertex shader processes subset of attributes of a vertex in a binning pass, where the subset of attributes include those that contribute to visibility determination and attributes that may benefit from being processed with a vertex shader that provides functional flexibility. A second, different vertex shader processes another subset of attributes of the vertex in the rendering pass.

Abstract translation: 本公开描述了在用于图形处理的合并体系结构中的不同图形处理期间使用两个顶点着色器的示例。 第一顶点着色器处理归并通过中顶点属性的子集，其中属性的子集包括对可见性确定有贡献的那些属性以及可能受益于提供功能灵活性的顶点着色器处理的属性。 第二个不同的顶点着色器处理渲染过程中顶点属性的另一个子集。

公开(公告)号：WO2017204910A1

公开(公告)日：2017-11-30

申请号：PCT/US2017/026842

申请日：2017-04-10

Applicant: QUALCOMM INCORPORATED

Inventor： CHEN, Lin ,  HAMMERSTONE, Richard ,  LIU, Jiaji ,  ZHANG, Chihong ,  GRUBER, Andrew Evan ,  DU, Yun

IPC: G06F12/0862 ,  G06F12/06 ,  G06F9/38 ,  G06F9/45 ,  G06T15/00

Abstract: A method for processing data in a graphics processing unit (GPU) including receiving an instance identifier for an instance and a shader program comprising a preamble code block and a main shader code block, assigning, the instance identifier to a general purpose register at wave creation, allocating address space within the constant memory for instance uniforms, and determining the preamble code block has not been executed and the wave is a first wave of the instance to be executed, based on determining the preamble code block has not been executed and the wave is the first wave to be executed, executing the preamble code block to store the plurality of instance uniforms in the constant memory and based, at least in part, on executing the preamble code block, executing the wave of the plurality of waves using at least one of the plurality of instance constants stored inconstant memory.

Abstract translation: 一种用于在图形处理单元（GPU）中处理数据的方法，所述方法包括：接收用于实例的实例标识符和包括前导码代码块和主着色器代码块的着色器程序;分配所述实例标识符 基于确定前导码而在波形创建时向通用寄存器分配恒定存储器内的地址空间以用于实例均匀化，并且确定前导码块还没有被执行并且波是要被执行的实例的第一波 块尚未被执行并且波是要被执行的第一波，执行前导码代码块以将多个实例统一性存储在常量存储器中并且至少部分地基于执行前导码代码块，执行波 使用所存储的不定内存的多个实例常量中的至少一个来执行所述多个波中的一个或多个

公开(公告)号：WO2017204909A1

公开(公告)日：2017-11-30

申请号：PCT/US2017/026835

申请日：2017-04-10

Applicant: QUALCOMM INCORPORATED

Inventor： CHEN, Lin ,  DU, Yun ,  GRUBER, Andrew Evan ,  JIAO, Guofang ,  YU, Chun ,  GARCIA GARCIA, David Rigel

IPC: G06T1/20

Abstract: A method for processing data in a graphics processing unit including receiving a code block of instructions common to a plurality of groups of threads of a shader, executing the code block of instructions common to the plurality of groups of threads of the shader creating a result by a group of threads of the plurality of groups of threads, storing the result of the code block of instructions common to the plurality of groups of threads of the shader in on-chip random access memory (RAM) accessible by each of the plurality of groups of threads, and upon a determination that storing the result of the code block of instructions common to the plurality of groups of threads of the shader has completed, returning the result of the code block of instructions common to the plurality of groups of threads of the shader from on-chip RAM.

Abstract translation: 一种用于处理图形处理单元中的数据的方法，所述方法包括：接收着色器的多个线程组所共有的指令的代码块;执行所述多个 着色器的线程通过多个线程组中的线程组创建结果，将片上随机存取存储器（RAM）中的着色器的多个线程组所共有的指令的代码块的结果存储在存储器中， 可由多个线程组中的每一个线程访问，并且在确定存储着色器的多个线程组共有的指令代码块的结果已完成时，将指令的代码块的结果返回到 来自片上RAM的着色器的多组线程。

公开(公告)号：WO2016077025A1

公开(公告)日：2016-05-19

申请号：PCT/US2015/055767

申请日：2015-10-15

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Liang ,  GRUBER, Andrew Evan ,  JIAO, Guofang ,  QI, Zhenyu ,  PITARYS, Gregory Steve ,  NOLAN, Scott William

IPC: G06T1/20

CPC classification number: G06T1/20 ,  G09G5/18 ,  G09G2330/022

Abstract: This disclosure describes an apparatus configured to process graphics data. The apparatus may include a fixed hardware pipeline configured to execute one or more functions on a current set of graphics data. The fixed hardware pipeline may include a plurality of stages including a bypassable portion of the plurality of stages. The apparatus may further include a shortcut circuit configured to route the current set of graphics data around the bypassable portion of the plurality of stages, and a controller positioned before the bypassable portion of the plurality of stages, the controller configured to selectively route the current set of graphics data to one of the shortcut circuit or the bypassable portion of the plurality of stages.

Abstract translation: 本公开描述了被配置为处理图形数据的装置。 该装置可以包括被配置为在当前图形数据集上执行一个或多个功能的固定硬件流水线。 固定硬件管线可以包括多个级，包括多个级的可旁路部分。 该装置还可以包括快速电路，其被配置为将当前图形数据集合围绕多个级的可旁路部分路由，以及位于多个级的可旁路部分之前的控制器，所述控制器被配置为选择性地路由当前集合 的图形数据提供给多个阶段的快捷电路或可旁路部分中的一个。

公开(公告)号：WO2015199997A1

公开(公告)日：2015-12-30

申请号：PCT/US2015/035332

申请日：2015-06-11

Applicant: QUALCOMM INCORPORATED

Inventor： DU, Yun ,  GRUBER, Andrew Evan ,  CHEN, Lin ,  JIAO, Guofang ,  YU, Chun

IPC: G09G5/36 ,  G06T1/60

CPC classification number: G06T1/60 ,  G06T15/80 ,  G09G5/363 ,  G09G2352/00 ,  G09G2360/06

Abstract: Techniques are described for determining whether data of a variable for each of a plurality of graphics items is same. If determined that the data is the same, the techniques store the data in a storage location of a specialized shared general purpose register that is associated with the variable.

Abstract translation: 描述了用于确定多个图形项目中的每一个的变量的数据是否相同的技术。 如果确定数据相同，则该技术将数据存储在与变量相关联的专用共享通用寄存器的存储位置中。

公开(公告)号：WO2022081293A1

公开(公告)日：2022-04-21

申请号：PCT/US2021/050670

申请日：2021-09-16

Applicant: QUALCOMM INCORPORATED

Inventor： BHIRAVABHATLA, Kalyan Kumar ,  GUMMIDIPUDI, Krishnaiah ,  SINGH, Ankit Kumar ,  GRUBER, Andrew Evan ,  AKKARAJU, Pavan Kumar ,  ALLA, Srihari Babu ,  NAGENDRA KUMAR, Jonnala Gadda ,  NIKAM, Vishwanath Shashikant

IPC: G06T15/40

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for configurable aprons for expanded binning. Aspects of the present disclosure include identifying one or more pixel tiles in at least one bin and determining edge information for each pixel tile of the one or more pixel tiles. The edge information may be associated with one or more pixels adjacent to each pixel tile. The present disclosure further describes determining whether at least one adjacent bin is visible based on the edge information for each pixel tile, where the at least one adjacent bin may be adjacent to the at least one bin.

公开(公告)号：WO2022076960A1

公开(公告)日：2022-04-14

申请号：PCT/US2021/071394

申请日：2021-09-08

Applicant: QUALCOMM INCORPORATED

Inventor： ALLA, Srihari Babu ,  RAMESH BABU, Adimulam ,  NAGENDRA KUMAR, Jonnala Gadda ,  SEETHARAMAIAH, Avinash ,  WANG, Tao ,  TANG, Xuefeng ,  FRISINGER, Thomas Edwin ,  GRUBER, Andrew Evan

IPC: G06T15/00 ,  G06T15/40 ,  G06T1/20 ,  G09G5/36

Abstract: The present disclosure relates to methods and apparatus for graphics processing. An example method generally includes receiving, at a graphics processing unit (GPU), a plurality of commands corresponding to a plurality of draws across a frame, each of the plurality of commands indicating a depth test direction with respect to a low-resolution depth (LRZ) buffer for the corresponding draw. The method generally includes maintaining, at the GPU, a LRZ status buffer to store a corresponding depth test direction for a first command in time of the plurality of commands processed by the GPU. The method generally includes disabling, at the GPU, use of the LRZ buffer for depth testing for any of the plurality of commands remaining unprocessed after processing a command of the plurality of commands having a different depth test direction than the corresponding depth test direction stored in the LRZ status buffer.

公开(公告)号：WO2022072104A1

公开(公告)日：2022-04-07

申请号：PCT/US2021/048433

申请日：2021-08-31

Applicant: QUALCOMM INCORPORATED

Inventor： ALLA, Srihari Babu ,  NAGENDRA KUMAR, Jonnala Gadda ,  SEETHARAMAIAH, Avinash ,  GRUBER, Andrew Evan ,  HAMMERSTONE, Richard ,  FRISINGER, Thomas Edwin ,  ARCHARD, Daniel

IPC: G06T15/00 ,  G06T1/60 ,  G06T1/20 ,  A63F13/52

Abstract: The present disclosure relates to methods and apparatus for hybrid rendering of video/graphics content by a graphics processing unit. The apparatus can configure the graphics processing unit of a display apparatus to perform multiple rendering passes for a frame of a scene to be displayed on a display device. Moreover, the apparatus can control the graphics processing unit to perform a first rendering pass of the multiple rendering passes to generate a first render target that is stored in either an on-chip graphics memory of the GPU or a system of the display apparatus. The apparatus can also control the graphics processing unit to perform a second rendering pass to generate a second render target that is alternatively stored in the system memory of the display apparatus or on-chip graphics memory of the GPU.

公开(公告)号：WO2017052750A2

公开(公告)日：2017-03-30

申请号：PCT/US2016/044060

申请日：2016-07-26

Applicant: QUALCOMM INCORPORATED

Inventor： KHANDELWAL, Shambhoo ,  XIA, Yang ,  TANG, Xuefeng ,  LIANG, Jian ,  WANG, Tao ,  GRUBER, Andrew Evan ,  DEMERS, Eric

IPC: G06T15/00

CPC classification number: G06T7/20 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T15/80 ,  G06T2200/04 ,  G06T2200/28

Abstract: A graphics processing unit (GPU) may determine a workload of a fragment shader program that executes on the GPU. The GPU may compare the workload of the fragment shader program to a threshold. In response to determining that the workload of the fragment shader program is lower than a specified threshold, the fragment shader program may process one or more fragments without the GPU performing early depth testing of the one or more fragments before the processing by the fragment shader program. The GPU may perform, after processing by the fragment shader program, late depth testing of the one or more fragments to result in one or more non-occluded fragments. The GPU may write pixel values for the one or more non-occluded fragments into a frame buffer.

Abstract translation: 图形处理单元（GPU）可以确定在GPU上执行的片段着色器程序的工作负载。 GPU可以将片段着色器程序的工作负载与阈值进行比较。 响应于确定片段着色器程序的工作负荷低于指定的阈值，片段着色器程序可以处理一个或多个片段，而GPU未在片段着色器程序处理之前执行对一个或多个片段的早期深度测试 。 在片段着色器程序处理之后，GPU可以执行一个或多个片段的深度深度测试以产生一个或多个未遮挡的片段。 GPU可以将一个或多个非遮挡片段的像素值写入帧缓冲器。