公开(公告)号：WO2022164604A1

公开(公告)日：2022-08-04

申请号：PCT/US2022/011176

申请日：2022-01-04

申请人： MICRON TECHNOLOGY, INC.

发明人： SREERAMANENI, Raghukiran ,  PENNEY, Daniel B.

IPC分类号： G11C7/02 ,  G11C7/10

摘要： An input receiver circuit for a signal line may receive inputs from other signal lines to mitigate crosstalk noise present on the signal line. In some examples, the input receiver circuit may include a transistor with a programmable width. In some examples, the input receiver circuit may include a bias current generator with a programmable current. The width and/or current may be programmed based on an amount of crosstalk noise introduced by the other signal line. In some examples, the input receiver circuit may include a resistance and/or a capacitance. In some examples the resistor and/or capacitor may be programmable. The resistance and/or capacitance may be programmed based on a duration of the crosstalk noise on the signal line.

公开(公告)号：WO2022010754A1

公开(公告)日：2022-01-13

申请号：PCT/US2021/040222

申请日：2021-07-02

申请人： INFINEON TECHNOLOGIES LLC

发明人： GEYARI, Eran ,  SHLOMO, Oren ,  SOFER, Yair ,  HARUSH, Avri

IPC分类号： H03K17/22 ,  G11C29/08 ,  H03K3/02 ,  H03K3/37 ,  H03K17/284 ,  H03L7/00 ,  G01K7/183 ,  G01K7/20 ,  G01R19/2506 ,  G05F1/648 ,  G11C7/02 ,  G11C7/1039 ,  G11C7/14 ,  G11C7/20 ,  H03K17/223 ,  H03K17/24 ,  H03K5/1252 ,  H03K5/153 ,  H03K5/19 ,  H03K5/2472

摘要： A system and method for protecting against a voltage glitch are provided. Generally, the system includes a reset-detector coupled to a supply voltage (VCC) and to a power-on-reset (POR) block, and a glitch-detector coupled to VCC and the reset-detector. The reset-detector is operable to provide a signal to the POR block to generate a global- reset-signal when VCC decreases below a minimum and remains low for at least a first time. The glitch-detector is operable to provide a glitch-signal to the reset-detector to cause it to provide the signal to the POR block when VCC decreases below the minimum and remains low for at least a second time, where the second time is less than the first. The reset-detector can further include a retention-circuit operable to recall a glitch-signal was received and signal the POR block when VCC is restored. Other embodiments are also disclosed.

公开(公告)号：WO2015094797A1

公开(公告)日：2015-06-25

申请号：PCT/US2014/069231

申请日：2014-12-09

申请人： SANDISK TECHNOLOGIES INC.

发明人： BHUIYAN, Ekram Hossain

IPC分类号： G06F13/38 ,  G06F1/32 ,  G11C7/02 ,  G06F13/16 ,  G11C5/14

CPC分类号： G06F1/3296 ,  G06F1/263 ,  G06F1/3203 ,  G06F13/16 ,  G11C5/14 ,  G11C7/1051 ,  G11C7/1069 ,  Y02D10/172 ,  Y02D50/20

摘要： A data storage device includes an interface. A method includes charging a voltage at a node of the interface using a first supply voltage. The method further includes partially discharging the voltage to a voltage supply node of the data storage device. The voltage supply node is associated with a second supply voltage.

摘要翻译： 数据存储装置包括接口。 一种方法包括使用第一电源电压对接口的节点处的电压进行充电。 该方法还包括将电压部分地放电到数据存储装置的电压供应节点。 电压供应节点与第二电源电压相关联。

公开(公告)号：WO2014176213A1

公开(公告)日：2014-10-30

申请号：PCT/US2014/034913

申请日：2014-04-22

申请人： INVENSAS CORPORATION

发明人： FISCH, David ,  PLANTS, William, C. ,  STALNAKER, Kent

IPC分类号： G11C7/02 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/06 ,  G11C11/4091

CPC分类号： G11C11/4091 ,  G11C7/00 ,  G11C7/02 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1069 ,  G11C7/1096 ,  G11C11/4087 ,  G11C11/4096 ,  G11C29/52

摘要： A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition.

摘要翻译： 一种存储数据的方法。 该方法包括提供包括存储器空间的可寻址存储器，其中存储器空间包括多个存储器单元。 该方法包括配置可寻址存储器，使得当将一个或多个外部数据状态的第一外部数据状态写入存储器空间时，存储器空间中的多个存储单元的大部分将内部数据值存储在优选偏置条件中， 其中所述第一外部数据状态与所述偏好条件相反。

公开(公告)号：WO2013075099A1

公开(公告)日：2013-05-23

申请号：PCT/US2012/065848

申请日：2012-11-19

申请人： EVERSPIN TECHNOLOGIES INC.

发明人： ALAM, Syed M. ,  ANDRE, Thomas

IPC分类号： G11C7/02

CPC分类号： G11C11/1673 ,  G11C7/00 ,  G11C7/10 ,  G11C7/1084 ,  G11C7/12 ,  G11C11/00 ,  G11C11/02 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1675 ,  G11C13/004 ,  G11C13/0069 ,  G11C29/50008

摘要： An analog read circuit measures the resistance of each of a plurality of bits in an array of resistive memory elements. Data stored within a latch determines whether to selectively enable the analog read circuit. In an alternate embodiment, a sense amplifier is coupled to the latch and the array, and the data stored in the latch determines whether to selectively enable the sense amplifier.

摘要翻译： 模拟读取电路测量电阻存储元件阵列中的多个位中的每一个的电阻。 存储在锁存器内的数据确定是否选择使能模拟读取电路。 在替代实施例中，读出放大器耦合到锁存器和阵列，并且存储在锁存器中的数据确定是否选择性地使能读出放大器。

公开(公告)号：WO2009075832A1

公开(公告)日：2009-06-18

申请号：PCT/US2008/013532

申请日：2008-12-09

申请人： SPANSION LLC ,  NIIMI, Masahiro ,  FURUYAMA, Takaaki ,  KATO, Kenta

发明人： NIIMI, Masahiro ,  FURUYAMA, Takaaki ,  KATO, Kenta

IPC分类号： G11C7/18 ,  G11C7/02

CPC分类号： G11C7/18 ,  G11C7/02 ,  G11C7/12 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/24 ,  G11C16/28

摘要： A nonvolatile storage device and control method are capable of supplying a ground potential to the source terminal of a memory cell while avoiding interference from a global bit line. The storage device has a first local bit line to which a first terminal of a memory cell is coupled; a second local bit line to which a second terminal of the memory cell is coupled; a first selector switch for coupling the first local bit line to a first global bit line; a second selector switch for coupling the second local bit line to a second global bit line; a third selector switch for coupling the first local bit line to a grounding line; and a fourth selector switch for coupling the second local bit line to the grounding line. The first and fourth selector switches or the second and third selector switches become conductive when reading a bit.

摘要翻译： 非易失性存储装置和控制方法能够在避免来自全局位线的干扰的同时向存储单元的源极提供接地电位。 存储装置具有第一本地位线，存储器单元的第一端耦合到该位线; 所述存储器单元的第二端子耦合到的第二局部位线; 第一选择器开关，用于将第一局部位线耦合到第一全局位线; 第二选择器开关，用于将第二局部位线耦合到第二全局位线; 用于将第一局部位线耦合到接地线的第三选择器开关; 以及用于将第二局部位线耦合到接地线的第四选择器开关。 读取位时，第一和第四选择器开关或第二和第三选择开关变为导通。

公开(公告)号：WO2007143268A2

公开(公告)日：2007-12-13

申请号：PCT/US2007/065616

申请日：2007-03-30

申请人： FREESCALE SEMICONDUCTOR INC. ,  ANDRE, Thomas W. ,  GARNI, Brad J. ,  NAHAS, Joseph J.

发明人： ANDRE, Thomas W. ,  GARNI, Brad J. ,  NAHAS, Joseph J.

IPC分类号： G11C7/02 ,  G11C5/14

CPC分类号： G11C7/02 ,  G11C7/062 ,  G11C11/1673

摘要： A memory circuit includes a sense amplifier (10) in which a single reference signal (OUTRFF) is compared to two data signals (OUT1 and OUT2) from two memory cells. The reference signal (OUTRFF) is generated from the combination of memory cells in opposite logic states. The data signal capacitance is matched to the reference signal capacitance. With reduced but matched capacitance both high speed and high sensitivity can be achieved.

摘要翻译： 存储电路包括读出放大器（10），其中单个参考信号（OUTRFF）与来自两个存储器单元的两个数据信号（OUT1和OUT2）进行比较。 参考信号（OUTRFF）是以相反逻辑状态的存储单元的组合产生的。 数据信号电容与参考信号电容匹配。 通过降低但匹配的电容，可以实现高速度和高灵敏度。

公开(公告)号：WO2007022382A3

公开(公告)日：2007-08-16

申请号：PCT/US2006032185

申请日：2006-08-16

申请人： NOVELICS ,  TERZIOGLU ESIN ,  WINOGRAD GIL I ,  AFGHAHI MORTEZA CYRUS

发明人： TERZIOGLU ESIN ,  WINOGRAD GIL I ,  AFGHAHI MORTEZA CYRUS

IPC分类号： G11C7/02

CPC分类号： G11C11/4091 ,  G11C7/02 ,  G11C7/065 ,  G11C7/12 ,  G11C11/401 ,  G11C11/4094 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C2207/2254 ,  H01L27/0207 ,  H01L27/10873 ,  H03K3/356034

摘要： In one embodiment, a sense amplifier includes: a differential amplifier adapted to amplify a voltage difference between a pair of bit lines; and a self-bias generation circuit adapted to reduce an offset bias in the differential amplifier with regard to the amplification of the voltage difference between the pair of bit lines.

摘要翻译： 在一个实施例中，读出放大器包括：差分放大器，适用于放大一对位线之间的电压差; 以及自偏置产生电路，其适于关于所述一对位线之间的电压差的放大来减小所述差分放大器中的偏置偏置。

公开(公告)号：WO2007027577A3

公开(公告)日：2007-07-05

申请号：PCT/US2006033480

申请日：2006-08-29

申请人： FREESCALE SEMICONDUCTOR INC ,  HUNTER BRADFORD L ,  ZHANG SHAYAN

发明人： HUNTER BRADFORD L ,  ZHANG SHAYAN

IPC分类号： G11C7/02

CPC分类号： G11C7/12 ,  G11C7/065 ,  G11C7/1048 ,  G11C7/18

摘要： A memory (100) includes first (116) and second (118) sense amplifiers, a first logic gate (120), a first three-state driver (130), and a latch (180). The first sense amplifier (116) is coupled to a first local data line and has an output terminal for providing a signal indicative of a state of a selected memory cell on the first local data line. The second sense amplifier (118) is coupled to a second local data line and has an output terminal for providing a signal indicative of a state of a selected memory cell on the second local data line. The first three- state driver (130) has a data input terminal coupled to the output terminal of the first logic gate (120), a control input terminal for receiving a first select signal, and an output terminal coupled to a global data line. The latch (180) has an input/output terminal coupled to the global data line (170).

摘要翻译： 存储器（100）包括第一（116）和第二（118）读出放大器，第一逻辑门（120），第一三状态驱动器（130）和锁存器（180）。 第一读出放大器（116）耦合到第一本地数据线，并且具有用于在第一本地数据线上提供指示所选存储器单元的状态的信号的输出端。 第二读出放大器（118）耦合到第二本地数据线，并且具有用于提供表示第二本地数据线上所选存储单元的状态的信号的输出端。 第一三态驱动器（130）具有耦合到第一逻辑门（120）的输出端的数据输入端，用于接收第一选择信号的控制输入端和耦合到全局数据线的输出端。 锁存器（180）具有耦合到全局数据线（170）的输入/输出端子。

公开(公告)号：WO2005041107A3

公开(公告)日：2005-12-08

申请号：PCT/IL2004000982

申请日：2004-10-27

申请人： SAIFUN SEMICONDUCTORS LTD ,  COHEN GUY

发明人： COHEN GUY

IPC分类号： G06F11/10 ,  G06K20060101 ,  G11C7/00 ,  G11C7/02 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  G11C16/28 ,  G11C16/30 ,  G11C16/34 ,  G11C17/00 ,  G11C29/00 ,  G11C29/24 ,  G11C29/50

CPC分类号： G11C11/5642 ,  G06F11/1008 ,  G11C16/28 ,  G11C16/30 ,  G11C16/3436 ,  G11C29/24 ,  G11C29/50 ,  G11C2029/0409 ,  G11C2029/5004 ,  G11C2211/5634

摘要： The present invention is a method, circuit and system for determining a reference voltage. Some embodiments of the present invention relate to a system, method and circuit for establishing a set of operating reference cells to be used in operating (e.g. reading) cells in an NVM block or array. As part of the present invention, at least a subset of cells of the NVM block or array may be read using each of two or more sets of test reference cells, where each set of test reference cells may generate or otherwise provide reference voltages at least slightly offset from each other set of test reference cells. For each set of test reference cells used to read the at least a subset of the NVM block, a read error rate may be calculated or otherwise determined. A set of test reference cells associated with a relatively low read error rate may be selected as the set of operating reference cells to be used in operating (e.g. reading) other cells, outside the subset of cells, in the NVM block or array. In a further embodiment, the selected set of test reference cells may be used to establish an operating set of reference cells having reference voltages substantially equal to those of the selected test set.

摘要翻译： 本发明是用于确定参考电压的方法，电路和系统。 本发明的一些实施例涉及用于建立在NVM块或阵列中操作（例如读取）单元中使用的一组操作参考单元的系统，方法和电路。 作为本发明的一部分，可以使用两组或更多组测试参考单元中的每一个读取NVM块或阵列的至少一个单元子集，其中每组测试参考单元可以生成或以其他方式提供参考电压 从每组其他测试参考单元略微偏移。 对于用于读取NVM块的至少一个子集的每组测试参考单元，可以计算或以其他方式确定读取错误率。 可以选择与相对低的读取错误率相关联的一组测试参考单元作为在NVM块或阵列中操作（例如读取）位于单元子集外部的其他单元的一组操作参考单元。 在进一步的实施例中，选定的一组测试参考单元可以用于建立具有基本上等于所选测试集的参考电压的参考电压的操作集合。