GENERALIZED CONFIGURABLE TRIGGER
    1.
    发明申请

    公开(公告)号:WO2019217193A1

    公开(公告)日:2019-11-14

    申请号:PCT/US2019/030373

    申请日:2019-05-02

    Abstract: A device for activating trigger data has a serial bus interface and a processing circuit coupled to the serial bus interface. The processing circuit is configured to receive a plurality of trigger data via a serial bus (902), receive a plurality of activation data via the serial bus (904), detect an activation scheme for activating a respective trigger data of the plurality of trigger data based on activation data corresponding to the respective trigger data (906), and activate the respective trigger data according to the detected activation scheme (908). If activated, each one of the plurality of trigger data respectively enables a corresponding operation to be performed at the device. Each one of the plurality of activation data respectively correspond to each one of the plurality of trigger data.

    RADIO FREQUENCY FRONT END DEVICES WITH MASKED WRITE
    2.
    发明申请
    RADIO FREQUENCY FRONT END DEVICES WITH MASKED WRITE 审中-公开
    带掩盖式写入的无线电频率前端装置

    公开(公告)号:WO2017070371A2

    公开(公告)日:2017-04-27

    申请号:PCT/US2016/057951

    申请日:2016-10-20

    CPC classification number: G06F13/28 G06F13/102 G06F13/16

    Abstract: Methods and apparatuses are described that facilitate the communication of data between a transmitter and a receiver across a serial bus interface. In one configuration, a transmitter generates a datagram based on a 16-bit address and a mask-and-data pair burst length, the 16-bit address including a most significant byte (MSB) and a least significant byte (LSB), compares the MSB to a receiver base address maintained in a shadow register, compares the mask-and-data pair burst length to a receiver masked-write burst length maintained in the shadow register, and sends the datagram to the receiver via the bus interface when: the MSB is equal to the receiver base address maintained in the shadow register, and the mask-and-data pair burst length is equal to the receiver masked-write burst length maintained in the shadow register.

    Abstract translation: 描述了便于通过串行总线接口在发射机和接收机之间进行数据通信的方法和设备。 在一种配置中,发送器基于16位地址和掩码与数据对突发长度生成数据报,该16位地址包括最高有效字节(MSB)和最低有效字节(LSB),比较 MSB与影子寄存器中保存的接收机基地址进行比较,将掩码与数据对突发长度与保存在影子寄存器中的接收机屏蔽写入突发长度进行比较,并在以下情况下通过总线接口将数据报发送给接收机: MSB等于影子寄存器中保存的接收器基地址,掩码和数据对的突发长度等于影子寄存器中保存的接收器屏蔽写突发长度。

    CONTROLLING COEXISTENT RADIO SYSTEMS IN A WIRELESS DEVICE

    公开(公告)号:WO2018232250A1

    公开(公告)日:2018-12-20

    申请号:PCT/US2018/037767

    申请日:2018-06-15

    Abstract: Disclosed aspects relate to methods and apparatus for coexistent radio frequency (RF) systems in a wireless device. Control of a wireless device includes detecting when a turn on signal is issued to a first radio system, and then controlling the second radio system to either modify the operation of receiver circuitry in the second radio system to protect components within that system, or modify transmit circuitry to stop transmissions for protecting components within one radio system potentially affected by transmission from the other radio system in the wireless device. Disclosed also is monitoring of transmission states of the radio systems based on reading messages between the first and second radio systems and issuing a notification message based thereon such that one of the radio systems may suspend monitoring of a transmit channel for permission to transmit in order to reduce power consumption due to such monitoring of the channel.

    TRIPLE-DATA-RATE TECHNIQUE FOR A SYNCHRONOUS LINK
    4.
    发明申请
    TRIPLE-DATA-RATE TECHNIQUE FOR A SYNCHRONOUS LINK 审中-公开
    一种同步链路的三数据速率技术

    公开(公告)号:WO2018026871A1

    公开(公告)日:2018-02-08

    申请号:PCT/US2017/044990

    申请日:2017-08-01

    Abstract: Systems, methods, and apparatus for transmitting additional information over a synchronous serial bus are described. A method performed at a transmitting device coupled to the serial bus includes providing first data in a data signal to be transmitted on a first wire of a multi-wire serial bus, providing a series of pulses in a clock signal to be transmitted on a second wire of a multi-wire serial bus, where each pulse has a rising edge and a falling edge, each edge being aligned with a different bit of the first data. The method may include encoding second data in the clock signal by controlling a duration of each pulse in the series of pulses based on a value of one or more bits of the second data, and transmitting the data signal and the clock signal over the serial bus.

    Abstract translation: 描述了用于通过同步串行总线传输附加信息的系统,方法和装置。 在耦合到串行总线的发送设备处执行的方法包括:提供要在多线串行总线的第一导线上发送的数据信号中的第一数据,在时钟信号中提供要在第二导线上发送的一系列脉冲 多线串行总线的导线,其中每个脉冲具有上升沿和下降沿,每个边沿与第一数据的不同位对齐。 该方法可以包括通过基于第二数据的一个或多个比特的值来控制该系列脉冲中的每个脉冲的持续时间来编码时钟信号中的第二数据,并且通过串行总线传输数据信号和时钟信号

    CLASSIFIER FOR RADIO FREQUENCY FRONT-END (RFFE) DEVICES
    5.
    发明申请
    CLASSIFIER FOR RADIO FREQUENCY FRONT-END (RFFE) DEVICES 审中-公开
    无线电频率前端(RFFE)设备分类器

    公开(公告)号:WO2013138005A1

    公开(公告)日:2013-09-19

    申请号:PCT/US2013/025755

    申请日:2013-02-12

    CPC classification number: H04B1/40 H04B1/005 H04L12/403 H04L41/0896

    Abstract: A method for classifying radio frequency front-end (RFFE) devices. The method includes enumerating a radio frequency front-end (RFFE) slave device according to at least one classifier bit within the RFFE slave device. The method also includes adjusting an RFFE control interface of an RFFE master device according to slave device configuration information determined from the at least one classifier bit within the RFFE slave device.

    Abstract translation: 一种用于对射频前端(RFFE)设备进行分类的方法。 该方法包括根据RFFE从设备中的至少一个分类器位置列举射频前端(RFFE)从设备。 该方法还包括根据从RFFE从设备中的至少一个分类器位确定的从设备配置信息调整RFFE主设备的RFFE控制接口。

    ULTRA-SHORT DATAGRAMS FOR LATENCY SENSITIVE RADIO FREQUENCY FRONT-END

    公开(公告)号:WO2019050773A1

    公开(公告)日:2019-03-14

    申请号:PCT/US2018/048872

    申请日:2018-08-30

    Abstract: Systems, methods, and apparatus for data communication are provided. A method performed by a device operating as a bus master may include transmitting a first pulse on a first wire of a multi-wire interface, transmitting a second pulse on a second wire of the multi-wire interface while the first pulse is present on the first wire of the multi-wire interface, and initiating a low-latency mode of communication immediately after termination of the first pulse. The second pulse may be shorter in duration than the first pulse.

    RADIO FREQUENCY FRONT END DEVICES WITH HIGH DATA RATE MODE
    8.
    发明申请
    RADIO FREQUENCY FRONT END DEVICES WITH HIGH DATA RATE MODE 审中-公开
    具有高数据速率模式的无线电频率前端装置

    公开(公告)号:WO2017070377A1

    公开(公告)日:2017-04-27

    申请号:PCT/US2016/057958

    申请日:2016-10-20

    Abstract: Methods and apparatuses are described that facilitate the communication of data between a transmitter and a receiver across a serial bus interface. In one configuration, a transmitter generates a datagram based on a register address, detects whether the register address is within a high data rate (HDR) access address range, and sends a payload of the datagram to the receiver according to a HDR mode when the register address is within the HDR access address range. In another configuration, the transmitter generates a datagram including at least a command field and a data field, sends the command field to the receiver according to a single data rate (SDR) mode, wherein the command field indicates a transition to a high data rate (HDR) mode for sending the data field, and sends the data field to the receiver according to the HDR mode.

    Abstract translation: 描述了便于通过串行总线接口在发射机和接收机之间进行数据通信的方法和设备。 在一种配置中,发送器基于寄存器地址生成数据报,检测寄存器地址是否在高数据速率(HDR)访问地址范围内,并且当数据报的有效负载根据HDR模式发送到接收器时 寄存器地址在HDR访问地址范围内。 在另一种配置中,发射机生成包括至少一个命令字段和数据字段的数据报,根据单数据速率(SDR)模式向接收机发送命令字段,其中命令字段指示向高数据速率 (HDR)模式发送数据字段,并根据HDR模式将数据字段发送给接收器。

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