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    SYSTEM AND METHOD OF USING A PREDICATE VALUE TO ACCESS A REGISTER FILE
    4.
    发明申请
    SYSTEM AND METHOD OF USING A PREDICATE VALUE TO ACCESS A REGISTER FILE 审中-公开

    公开(公告)号：WO2006110905A3

    公开(公告)日：2006-10-19

    申请号：PCT/US2006/014173

    申请日：2006-04-11

    Applicant: QUALCOMM INCORPORATED ,  AHMED, Muhammad ,  PLONDKE, Erich ,  CODRESCU, Lucian ,  ANDERSON, William C.

    Inventor： AHMED, Muhammad ,  PLONDKE, Erich ,  CODRESCU, Lucian ,  ANDERSON, William C.

    IPC: G06F9/38

    Abstract: A processor device is disclosed and includes a memory unit and at least one interleaved multi-threading instruction pipeline. The interleaved multi-threading instruction pipeline utilizes a number of clock cycles that is less than an instruction issue rate for each of a plurality of program threads that are stored within the memory unit. The memory unit includes six instruction caches. Further, the processor device includes six register files and each of the six register files is associated with one of the six instruction caches. Each of the plurality of program threads is associated with one of the six register files. Further, each of the six program threads includes a plurality of instructions and each of the plurality of instructions is stored within one of the six instruction caches of the memory.

    INSTRUCTION MEMORY UNIT AND METHOD OF OPERATION
    5.
    发明申请
    INSTRUCTION MEMORY UNIT AND METHOD OF OPERATION 审中-公开
    指令记忆单元和操作方法

    公开(公告)号：WO2006110886A2

    公开(公告)日：2006-10-19

    申请号：PCT/US2006/013948

    申请日：2006-04-11

    Applicant: QUALCOMM Incorporated ,  AHMED, Muhammad ,  CODRESCU, Lucian ,  PLONDKE, Erich ,  ANDERSON, William C. ,  LESTER, Robert Allan ,  JONES, Phillip M.

    Inventor： AHMED, Muhammad ,  CODRESCU, Lucian ,  PLONDKE, Erich ,  ANDERSON, William C. ,  LESTER, Robert Allan ,  JONES, Phillip M.

    CPC classification number: G06F9/325 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/381

    Abstract: An instruction memory unit comprises a first memory structure operable to store program instructions, and a second memory structure operable to store program instructions fetched from the first memory structure, and to issue stored program instructions for execution. The second memory structure is operable to identify a repeated issuance of a forward program redirect construct, and issue a next program instruction already stored in the second memory structure if a resolution of the forward branching instruction is identical to a last resolution of the same. The second memory structure is further operable to issue a backward program redirect construct, determine whether a target instruction is stored in the second memory structure, issue the target instruction if the target instruction is stored in the second memory structure, and fetch the target instruction from the first memory structure if the target instruction is not stored in the second memory structure.

    Abstract translation: 指令存储单元包括可操作以存储程序指令的第一存储器结构，以及可操作以存储从第一存储器结构提取的程序指令并且发出用于执行的存储的程序指令的第二存储器结构。 如果前向分支指令的分辨率与其最后一个分辨率相同，则第二存储器结构可操作以识别正向程序重定向构造的重复发出，并发出已经存储在第二存储器结构中的下一个程序指令。 第二存储器结构还可操作以发出反向程序重定向结构，确定目标指令是否存储在第二存储器结构中，如果目标指令存储在第二存储器结构中，则发出目标指令，并从 如果目标指令没有存储在第二存储器结构中的第一存储器结构。

    METHOD AND SYSTEM FOR VARIABLE THREAD ALLOCATION AND SWITCHING IN A MULTITHREADED PROCESSOR
    6.
    发明申请
    METHOD AND SYSTEM FOR VARIABLE THREAD ALLOCATION AND SWITCHING IN A MULTITHREADED PROCESSOR 审中-公开

    公开(公告)号：WO2006102668A3

    公开(公告)日：2006-09-28

    申请号：PCT/US2006/011175

    申请日：2006-03-23

    Applicant: QUALCOMM INCORPORATED ,  AHMED, Muhammad ,  JAMIL, Sujat ,  PLONDKE, Erich ,  CODRESCU, Lucian ,  ANDERSON, William C.

    Inventor： AHMED, Muhammad ,  JAMIL, Sujat ,  PLONDKE, Erich ,  CODRESCU, Lucian ,  ANDERSON, William C.

    IPC: G06F9/38

    Abstract: Techniques for processing transmissions in a communications (e.g., CDMA) system. An aspect of the disclosed subject matter includes a method for processing instructions on a multithreaded processor. The multithreaded processor processes a plurality of threads via a plurality of processor pipelines. The method includes the step determining the operating frequency, F, at which the multithreaded processor operates. Then, the method determines a variable thread switch timeout state for triggering the switching of the processing among the plurality of active threads. The variable thread switch timeout state varies so that each of the plurality of active threads operates at a frequency of an allocated portion of the frequency, F. The allocated portion at which the active threads operate is determined at least in part in order to optimize the operation of the multithreaded processor. The method furtherswitches the processing from a first one of the active threads to a next one of the active threads upon the occurrence of the variable thread switch timeout state.

    METHOD AND SYSTEM FOR ENCODING VARIABLE LENGTH PACKETS WITH VARIABLE INSTRUCTION SIZES
    7.
    发明申请
    METHOD AND SYSTEM FOR ENCODING VARIABLE LENGTH PACKETS WITH VARIABLE INSTRUCTION SIZES 审中-公开
    用于编写具有可变指令尺寸的可变长度分组的方法和系统

    公开(公告)号：WO2006102664A2

    公开(公告)日：2006-09-28

    申请号：PCT/US2006/011171

    申请日：2006-03-23

    Applicant: QUALCOMM INCORPORATED ,  CODRESCU, Lucian ,  PLONDKE, Erich ,  AHMED, Muhammad ,  ANDERSON, William C.

    Inventor： CODRESCU, Lucian ,  PLONDKE, Erich ,  AHMED, Muhammad ,  ANDERSON, William C.

    IPC: G06F9/30

    CPC classification number: G06F9/30149 ,  G06F9/3853

    Abstract: Techniques for processing transmissions in a communications (e.g., CDMA) system. The method and system encode and process instructions of mixed lengths (e.g., 16 bits and 32 bits) and instruction packets including instructions of mixed lengths. This includes encoding a plurality of instructions of a first length and a plurality of instructions of a second length. The method and system encode a header having at least one instruction length bit. The instruction bit distinguishes between instructions of the first length and instructions of the second length for an associated DSP to process in a mixed stream. The method and system distinguish between the instructions of the first length and the instructions of the second length according to the contents of the instruction length bits. The header further includes bits for distinguishing between instructions of varying lengths in an instruction packet.

    Abstract translation: 用于在通信（例如，CDMA）系统中处理传输的技术。 该方法和系统编码和处理混合长度（例如，16位和32位）的指令以及包括混合长度指令的指令包。 这包括编码具有第二长度的第一长度和多个指令的多个指令。 该方法和系统对具有至少一个指令长度位的报头进行编码。 指令位区分第一长度的指令和第二长度的指令，以使相关的DSP在混合流中进行处理。 方法和系统根据指令长度位的内容区分第一长度的指令和第二长度的指令。 标题还包括用于区分指令包中不同长度的指令的位。

    ENCODING HARDWARE END LOOP INFORMATION ONTO AN INSTRUCTION
    10.
    发明申请
    ENCODING HARDWARE END LOOP INFORMATION ONTO AN INSTRUCTION 审中-公开
    编写硬件结束信息到指令

    公开(公告)号：WO2007133893A1

    公开(公告)日：2007-11-22

    申请号：PCT/US2007/067134

    申请日：2007-04-20

    Applicant: QUALCOMM Incorporated ,  PLONDKE, Erich ,  LESTER, Robert, Allan ,  CODRESCU, Lucian ,  AHMED, Muhammad

    Inventor： PLONDKE, Erich ,  LESTER, Robert, Allan ,  CODRESCU, Lucian ,  AHMED, Muhammad

    IPC: G06F9/30 ,  G06F9/38

    CPC classification number: G06F9/30149 ,  G06F9/325 ,  G06F9/3853 ,  G06F9/3885

    Abstract: Methods and apparatus for encoding information regarding a hardware loop of a set of packets is provided, each packet (400) containing instructions. The information is encoded into one or more bits of at least one instruction (300) in the set of packets. The information may indicate whether a packet is or is not an end packet of the loop. Information regarding two hardware loops may be encoded where information regarding the first loop is encoded into an instruction at a first position in each packet and information regarding the second loop is encoded into an instruction at a second position in each packet. End instruction information may be encoded into an instruction not having encoded loop information at the same bit positions reserved for the encoded loop information, the end instruction information indicating whether an instruction is the last instruction of a packet and the length of a packet.

    Abstract translation: 提供了用于编码关于一组分组的硬件循环的信息的方法和装置，每个分组（400）包含指令。 信息被编码成该组分组中的至少一个指令（300）的一个或多个位。 信息可以指示分组是否是循环的结束分组。 关于两个硬件循环的信息可以被编码，其中关于第一循环的信息被编码为每个分组中的第一位置处的指令，并且关于第二循环的信息被编码为每个分组中的第二位置处的指令。 结束指令信息可以被编码为在编码环路信息保留的相同位位置处不具有编码环路信息的指令，表示指令是分组的最后指令还是分组长度的结束指令信息。

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