Abstract:
A wireless communication device includes: a housing configured to retain components of the wireless communication device; an antenna unit configured to receive first free-space millimeter-wave signals and convert these signals to first electronic millimeter-wave signals; a processor disposed in the housing; and front-end circuitry communicatively coupled to the antenna unit, the front-end circuitry coupled to the processor by at least one transmission line; where the front-end circuitry is configured to: receive the first electronic millimeter-wave signals from the antenna unit; convert the first electronic millimeter-wave signals to first reduced-frequency signals each having a lower frequency than the first electronic millimeter-wave signals; and convey the first reduced-frequency signals over a same transmission line of the at least one transmission line in a multiplexed manner with different ones of the first reduced-frequency signals having different conveyance characteristics such that the different ones of the first reduced-frequency signals can be separately processed.
Abstract:
A method includes generating a first signal based on a difference between a first frequency of a first voltage controlled oscillator (VCO) and a second frequency of a second VCO. The method further includes determining a gain of the first VCO at least partially based on the first signal.
Abstract:
A circuit (300) for generating a local oscillator signal (330out) includes: at least one divider module (320) configured to receive an input signal (342) and divide a frequency of the input signal (312) by a division ratio (340); and a load circuit (330) coupled to the at least one divider module (320), the load circuit (340) configured to provide balanced current pulses that substantially reduce at least a portion of harmonic current ripples in the local oscillator signal (330 out).
Abstract:
A dual-band voltage controlled oscillator (VCO) includes: a first oscillator circuit including a first inductor; a second oscillator circuit including a second inductor; a first mode switch configured to electrically connect or disconnect a first output terminal of the first oscillator circuit and a first output terminal of the second oscillator circuit; a second mode switch configured to electrically connect or disconnect a second output terminal of the first oscillator circuit and a second output terminal of the second oscillator circuit; a third mode switch configured to electrically connect or disconnect a first terminal of the first inductor and a first terminal of the second inductor; and a fourth mode switch configured to electrically connect or disconnect a second terminal of the first inductor and a second terminal of the second inductor.
Abstract:
A high-speed current-mode clock driver includes feedback circuitry to maintain the voltage swing of a biasing node within a defined range. The current-mode clock driver includes a PMOS and an NMOS transistor receiving an oscillating signal at their gate terminals. The drain terminals of the PMOS and NMOS transistors are respectively coupled to input terminals of first and second variable conductivity circuits whose output terminals are coupled to a common node. A control circuit increases the conductivities of the first and second variable conductivity circuits in response to decreases in voltage swing of the common node, and decreases the conductivities of the first and second variable conductivity circuits in response to increases in voltage swing of the common node. The first and second variable conductivity circuits are optionally PMOS and NMOS transistors respectively.