公开(公告)号：WO2016048651A1

公开(公告)日：2016-03-31

申请号：PCT/US2015/048959

申请日：2015-09-08

Applicant: QUALCOMM INCORPORATED

Inventor： STEMPEL, Brian Michael ,  DIEFFENDERFER, James Norris ,  MCILVAINE, Michael Scott ,  BROWN, Melinda

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30072 ,  G06F9/30149 ,  G06F9/38 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3885

Abstract: Systems and methods for dependency-prediction include executing instructions in an instruction pipeline of a processor and detecting a conditionality-imposing control instruction, such as an If-Then (IT) instruction, which imposes dependent behavior on a conditionality block size of one or more dependent instructions. Prior to executing a first instruction, a dependency-prediction is made to determine if the first instruction is a dependent instruction of the conditionality-imposing control instruction, based on the conditionality block size and one or more parameters of the instruction pipeline. The first instruction is executed based on the dependency-prediction. When the first instruction is dependency-mispredicted, an associated dependency-misprediction penalty is mitigated. If the first instruction is a branch instruction, the mitigation involves training a branch prediction tracking mechanism to correctly dependency-predict future occurrences of the first instruction.

Abstract translation: 用于依赖性预测的系统和方法包括在处理器的指令流水线中执行指令，并且检测诸如If-Then（IT）指令之类的有条件的控制指令，该指令将依赖行为强加于一个或多个 依赖说明。 在执行第一指令之前，基于条件块大小和指令流水线的一个或多个参数，进行依赖性预测以确定第一指令是否是条件施加控制指令的依赖指令。 基于依赖关系预测执行第一指令。 当第一条指令是依赖性错误预测时，减轻相关的依赖关系错误估计。 如果第一指令是分支指令，则缓解涉及训练分支预测跟踪机制以正确依赖 - 预测第一指令的将来出现。

公开(公告)号：WO2009046326A1

公开(公告)日：2009-04-09

申请号：PCT/US2008/078789

申请日：2008-10-03

Applicant: QUALCOMM INCORPORATED ,  DIEFFENDERFER, James Norris ,  STEMPEL, Brian Michael ,  SMITH, Rodney Wayne

Inventor： DIEFFENDERFER, James Norris ,  STEMPEL, Brian Michael ,  SMITH, Rodney Wayne

IPC: G06F9/38

CPC classification number: G06F9/3842 ,  G06F9/3806 ,  G06F9/3861

Abstract: Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively executed following a mispredicted branch. This condition is detected by maintaining a count of the total number of uncommitted link stack write instructions in the pipeline, and a count of the number of uncommitted link stack write instructions ahead of each branch instruction. When a branch is evaluated and determined to have been mispredicted, the count associated with it is compared to the total count. A discrepancy indicates a link stack write instruction was speculatively issued into the pipeline after the mispredicted branch instruction, and pushed a link address onto the link stack. The prior link address is restored to the link stack from the link stack restore buffer.

Abstract translation: 每当链接地址被写入链接堆栈时，链接堆栈条目的先前值被保存，并且在错误预测的分支之后推测地执行链路堆叠推送操作之后被还原到链路栈。 通过维持流水线中未提交的链路堆栈写入指令的总数的计数以及每个分支指令之前的未提交的链路栈写入指令的数量的计数来检测该条件。 当分支被评估并确定为被误判时，将与之相关联的计数与总计数进行比较。 一个差异表示在错误预测的分支指令之后推测发出链路堆栈写入指令，并将链路地址推送到链路堆栈上。 链路堆栈恢复缓冲区中的链路栈恢复到先前的链路地址。

公开(公告)号：WO2007130798A1

公开(公告)日：2007-11-15

申请号：PCT/US2007/067057

申请日：2007-04-20

Applicant: QUALCOMM Incorporated ,  SMITH, Rodney Wayne ,  STEMPEL, Brian Michael

Inventor： SMITH, Rodney Wayne ,  STEMPEL, Brian Michael

IPC: G06F9/30 ,  G06F9/318

CPC classification number: G06F9/30149 ,  G06F9/30152 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/3802 ,  G06F9/382

Abstract: A pre-decoder in a variable instruction length processor indicates properties of instructions in pre-decode bits stored in an instruction cache with the instructions. When all the encodings of pre-decode bits associate with one length instruction are defined, a property of an instruction of that length may be indicated by altering the instruction to emulate an instruction of a different length, and encoding the property in the pre-decode bits associated with instructions of the different length. One example of a property that may be so indicated is an undefined instruction.

Abstract translation: 可变指令长度处理器中的预解码器指示存储在具有指令的指令高速缓存中的预解码位中的指令的特性。 当预解码位的所有编码与一个长度指令相关联时，可以通过改变指令来模拟不同长度的指令来指示该长度的指令的属性，并且在预解码中编码该属性 与不同长度的指令相关联的位。 可能如此指示的属性的一个示例是未定义的指令。

公开(公告)号：WO2014085683A1

公开(公告)日：2014-06-05

申请号：PCT/US2013/072372

申请日：2013-11-27

Applicant: QUALCOMM INCORPORATED

Inventor： DIEFFENDERFER, James Norris ,  MORROW, Michael William ,  MCILVAINE, Michael Scott ,  STREETT, Daren Eugene ,  REDDY, Vimal K. ,  STEMPEL, Brian Michael

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3808 ,  G06F9/30054

Abstract: Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce pipeline bubbles, and related systems, methods, and computer-readable media are disclosed. In one embodiment, a method of establishing a BTIC entry includes detecting a subroutine call in an execution pipeline. In response, at least one instruction fetched sequential to the subroutine call is written as a branch target instruction in a BTIC entry for a subroutine return. A next instruction fetch address is calculated, and is written into a next instruction fetch address field in the BTIC entry. In this manner, the BTIC may provide correct branch target instruction and next instruction fetch address data for the subroutine return, even if the subroutine return is encountered for the first time or the subroutine is called from different calling locations.

Abstract translation: 建立用于子程序的分支目标指令缓存（BTIC）条目返回以减少管道气泡，以及相关系统，方法和计算机可读介质。 在一个实施例中，建立BTIC条目的方法包括检测执行流水线中的子程序调用。 作为响应，在子程序返回的BTIC条目中写入与子程序调用顺序取得的至少一个指令作为分支目标指令。 计算下一个指令提取地址，并将其写入BTIC条目中的下一个指令获取地址字段。 以这种方式，即使第一次遇到子程序返回或从不同的呼叫位置调用子程序，BTIC可以为子程序返回提供正确的分支目标指令和下一个指令获取地址数据。

公开(公告)号：WO2013170080A1

公开(公告)日：2013-11-14

申请号：PCT/US2013/040417

申请日：2013-05-09

Applicant: QUALCOMM INCORPORATED

Inventor： DEBRUYNE, Leslie, Mark ,  DIEFFENDERFER, James, Norris ,  MCILVAINE, Michael Scott ,  STEMPEL, Brian Michael

IPC: G06F12/08 ,  G06F12/14 ,  G06F9/30

CPC classification number: G06F12/0875 ,  G06F12/0886 ,  G06F12/1416 ,  G06F12/145

Abstract: Systems and methods are disclosed for maintaining an instruction cache including extended cache lines and page attributes for main cache line portions of the extended cache lines and, at least for one or more predefined potential page-crossing instruction locations, additional page attributes for extra data portions of the corresponding extended cache lines. In addition, systems and methods are disclosed for processing page-crossing instructions fetched from an instruction cache having extended cache lines.

Abstract translation: 公开了用于维护包括用于扩展高速缓存线的主高速缓存行部分的扩展高速缓存行和页面属性的指令高速缓存的系统和方法，并且至少对于一个或多个预定义的潜在交叉指令位置，用于附加数据部分的附加页面属性 的相应扩展缓存行。 此外，公开了用于处理从具有扩展高速缓存线的指令高速缓存取出的交叉指令的系统和方法。

公开(公告)号：WO2008039975A1

公开(公告)日：2008-04-03

申请号：PCT/US2007/079864

申请日：2007-09-28

Applicant: QUALCOMM Incorporated ,  SMITH, Rodney Wayne ,  STEMPEL, Brian Michael

Inventor： SMITH, Rodney Wayne ,  STEMPEL, Brian Michael

IPC: G06F9/38

CPC classification number: G06F9/30149 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3806 ,  G06F9/3844

Abstract: In a processor executing instructions in at least a first instruction set execution mode having a first minimum instruction length and a second instruction set execution mode having a smaller, second minimum instruction length, line and counter index addresses are formed that access every counter in a branch history table (BHT), and reduce the number of index address bits that are multiplexed based on the current instruction set execution mode. In one embodiment, counters within a BHT line are arranged and indexed in such a manner that half of the BHT can be powered down for each access in one instruction set execution mode.

Abstract translation: 在处理器执行至少具有第一最小指令长度的第一指令集执行模式和具有较小的第二最小指令长度的第二指令集执行模式的指令时，形成行和每个计数器索引地址，以访问分支中的每个计数器 历史表（BHT），并根据当前指令集执行模式减少多路复用的索引地址位的数量。 在一个实施例中，BHT线内的计数器被布置和索引，使得一个BHT的一半可以在一个指令集执行模式中为每个访问断电。

公开(公告)号：WO2006125219A3

公开(公告)日：2006-11-23

申请号：PCT/US2006/019788

申请日：2006-05-18

Applicant: QUALCOMM INCORPORATED ,  SMITH, Rodney Wayne ,  STEMPEL, Brian Michael

Inventor： SMITH, Rodney Wayne ,  STEMPEL, Brian Michael

IPC: G06F9/38 ,  G06F9/318

Abstract: A method and apparatus for caching instructions for a processor having multiple operating states. At least two of the operating states of the processor supporting different instruction sets. A block of instructions may be retrieved from memory while the processor is operating in one of the states. The instructions may be pre-decoded in accordance with said one of the states and loaded into cache. The processor, or another entity, may be used to determine whether the current state of the processor is the same as said one of the states used to pre-decode the instructions when one of the pre-decoded instructions in the cache is needed by the processor.

公开(公告)号：WO2020046846A1

公开(公告)日：2020-03-05

申请号：PCT/US2019/048209

申请日：2019-08-26

Applicant: QUALCOMM INCORPORATED

Inventor： YEN, Luke ,  CHOUDHARY, Niket ,  GHOSHAL, Pritha ,  SPEIER, Thomas Philip ,  STEMPEL, Brian Michael ,  MCAVOY, William James ,  EIBL, Patrick

IPC: G06F12/0888 ,  G06F12/0817

Abstract: A method, apparatus, and system for prefetching exclusive cache coherence state for store instructions is disclosed. An apparatus may comprise a cache and a gather buffer coupled to the cache. The gather buffer may be configured to store a plurality of cache lines, each cache line of the plurality of cache lines associated with a store instruction. The gather buffer may be further configured to determine whether a first cache line associated with a first store instruction should be allocated in the cache. If the first cache line associated with the first store instruction is to be allocated in the cache, the gather buffer is configured to issue a pre-write request to acquire exclusive cache coherency state to the first cache line associated with the first store instruction.

公开(公告)号：WO2013163161A1

公开(公告)日：2013-10-31

申请号：PCT/US2013/037768

申请日：2013-04-23

Applicant: QUALCOMM INCORPORATED

Inventor： BROWN, Melinda J. ,  MORROW, Michael William ,  DIEFFENDERFER, James Norris ,  STEMPEL, Brian Michael ,  MCILVAINE, Michael Scott

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3017 ,  G06F9/30018 ,  G06F9/3838

Abstract: Eliminating redundant masking operations in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first instruction in an instruction stream indicating an operation writing a value to a first register is detected by an instruction processing circuit, the value having a value size less than a size of the first register. The circuit also detects a second instruction in the instruction stream indicating a masking operation on the first register. The masking operation is eliminated upon a determination that the masking operation indicates a read operation and a write operation on the first register and has an identity mask size equal to or greater than the value size. In this manner, the elimination of the masking operation avoids potential read-after-write hazards and improves performance of a CPU by removing redundant operations from an execution pipeline.

Abstract translation: 公开了在指令处理电路和相关处理器系统，方法和计算机可读介质中消除冗余掩蔽操作。 在一个实施例中，由指令处理电路检测指示将值写入第一寄存器的操作的指令流中的第一指令，该值具有小于第一寄存器的大小的值。 电路还检测指示流中指示在第一寄存器上的屏蔽操作的第二指令。 在确定掩蔽操作指示对第一寄存器的读取操作和写入操作并且具有等于或大于值大小的身份掩码大小的情况下，屏蔽操作被消除。 以这种方式，消除掩蔽操作可避免潜在的写后危害，并通过从执行流水线中删除冗余操作来提高CPU性能。

公开(公告)号：WO2007101214A1

公开(公告)日：2007-09-07

申请号：PCT/US2007/062904

申请日：2007-02-27

Applicant: QUALCOMM INCORPORATED ,  DIEFFENDERFER, James Norris ,  MANDZAK, David John ,  SMITH, Rodney Wayne ,  STEMPEL, Brian Michael

Inventor： DIEFFENDERFER, James Norris ,  MANDZAK, David John ,  SMITH, Rodney Wayne ,  STEMPEL, Brian Michael

IPC: G06F9/38

CPC classification number: G06F9/3844 ,  G06F9/30054 ,  G06F9/3806 ,  G06F9/3842 ,  G06F9/3861

Abstract: A link stack in a processor is repaired in response to a procedure return address misprediction error. In one example, a link stack for use in a processor is repaired by detecting an error in a procedure return address value retrieved from the link stack and skipping a procedure return address value currently queued for retrieval from the link stack responsive to detecting the error. In one or more embodiments, a link stack circuit comprises a link stack and a link stack pointer. The link stack is configured to store a plurality of procedure return address values. The link stack pointer is configured to skip a procedure return address value currently queued for retrieval from the link stack responsive to an error detected in a procedure return address value previously retrieved from the link stack.

Abstract translation: 响应于过程返回地址错误预测错误，处理器中的链路堆栈被修复。 在一个示例中，通过检测从链接堆栈检索到的过程返回地址值中的错误来修复处理器中使用的链接栈，并且响应于检测到错误，跳过当前排队等待从链接堆栈检索的过程返回地址值。 在一个或多个实施例中，链路栈电路包括链路栈和链路栈指针。 链路栈被配置为存储多个过程返回地址值。 链路堆栈指针被配置为响应于先前从链路栈检索的过程返回地址值中检测到的错误，跳过当前排队等待从链路栈检索的过程返回地址值。