公开(公告)号：WO2018038805A1

公开(公告)日：2018-03-01

申请号：PCT/US2017/039636

申请日：2017-06-28

Applicant: QUALCOMM INCORPORATED

Inventor： SUH, Jungwon ,  CHUN, Dexter ,  LO, Haw-Jing

IPC: G06F13/16

Abstract: Systems and method are directed to reducing power consumption of data transfer between a processor and a memory. A data to be transferred on a data bus between the processor and the memory is checked for a first data pattern, and if the first data pattern is present, transfer of the first data pattern is suppressed on the data bus. Instead, a first address corresponding to the first data pattern is transferred on a second bus between the processor and the memory. The first address is smaller than the first data pattern. The processor comprises a processor-side first-in-first-out (FIFO) and the memory comprises a memory-side FIFO, wherein the first data pattern is present at the first address in the processor-side FIFO and at the first address in the memory-side FIFO.

Abstract translation: 系统和方法致力于减少处理器和存储器之间的数据传输的功耗。 检查要在处理器和存储器之间的数据总线上传送的数据的第一数据模式，并且如果存在第一数据模式，则在数据总线上抑制第一数据模式的传送。 而是，在第二总线上在处理器和存储器之间传送对应于第一数据模式的第一地址。 第一个地址小于第一个数据模式。 所述处理器包括处理器侧先进先出（FIFO），并且所述存储器包括存储器侧FIFO，其中所述第一数据模式存在于所述处理器侧FIFO中的所述第一地址处并且处于所述第一地址处 存储器端FIFO。

公开(公告)号：WO2017152005A1

公开(公告)日：2017-09-08

申请号：PCT/US2017/020582

申请日：2017-03-03

Applicant: QUALCOMM INCORPORATED

Inventor： SUH, Jungwon ,  CHUN, Dexter, Tamio ,  LO, Michael, Hawjing

IPC: G06F13/16 ,  G06F1/32

Abstract: Power saving techniques for memory systems are disclosed. In particular, exemplary aspects of the present disclosure contemplate taking advantage of patterns that may exist within memory elements and eliminating duplicative data transfers. Specifically, if data is repetitive, instead of sending the same data repeatedly, the data may be sent only a single time with instructions that cause the data to be replicated at a receiving end to restore the data to its original repeated state. By reducing the amount of data that is transferred between a host and a memory element, power consumption is reduced.

Abstract translation: 公开了用于存储器系统的省电技术。 具体而言，本公开的示例性方面考虑利用可能存在于存储器元件内的模式并消除重复的数据传输。 具体来说，如果数据是重复的，而不是重复发送相同的数据，则数据可以只发送一次指令，使得数据在接收端被复制以将数据恢复到其原始重复状态。 通过减少在主机和存储器元件之间传输的数据量，功耗得以降低。

公开(公告)号：WO2017087076A1

公开(公告)日：2017-05-26

申请号：PCT/US2016/054175

申请日：2016-09-28

Applicant: QUALCOMM INCORPORATED

Inventor： SUH, Jungwon ,  WEST, David Ian

IPC: G06F11/10

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1048 ,  G11C29/52

Abstract: A memory device may include link error correction code (ECC) decoder and correction circuitry. The ECC decoder and correction circuitry may be arranged in a write path and configured for link error detection and correction of write data received over a data link. The memory device may also include memory ECC encoder circuitry. The memory ECC encoder circuitry may be arranged in the write path and configured for memory protection of the write data during storage in a memory array.

Abstract translation: 存储器件可以包括链接错误校正码（ECC）解码器和校正电路。 ECC解码器和校正电路可以被布置在写入路径中并且被配置用于通过数据链路接收的写入数据的链路错误检测和校正。 存储器装置还可以包括存储器ECC编码器电路。 存储器ECC编码器电路可以被布置在写入路径中并且被配置用于在存储在存储器阵列期间的写入数据的存储器保护。

公开(公告)号：WO2017087075A1

公开(公告)日：2017-05-26

申请号：PCT/US2016/054162

申请日：2016-09-28

Applicant: QUALCOMM INCORPORATED

Inventor： WEST, David Ian ,  SUH, Jungwon

IPC: G06F11/10

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1048 ,  G11C29/52

Abstract: A memory sub-system may include a memory controller having error correction code (ECC) encoder/decoder logic. The memory controller may be configured to embed link ECC parity bits in unused data mask bits and/or in a mask write data during a mask write operation. The memory controller may also be configured to protect at least a location of the link ECC parity bits during the mask write operation.

Abstract translation: 存储器子系统可以包括具有纠错码（ECC）编码器/解码器逻辑的存储器控​​制器。 存储器控制器可以被配置为在掩码写入操作期间将链接ECC奇偶校验位嵌入到未使用的数据掩码位中和/或掩码写入数据中。 存储器控制器还可以被配置为在掩码写入操作期间至少保护链接ECC奇偶校验位的位置。

公开(公告)号：WO2015005975A1

公开(公告)日：2015-01-15

申请号：PCT/US2014/038845

申请日：2014-05-20

Applicant: QUALCOMM INCORPORATED

Inventor： SRIRAMAGIRI, Deepti Vijayalakshmi ,  SUH, Jungwon ,  DONG, Xiangyu

IPC: G11C11/406 ,  G06F13/16

CPC classification number: G11C11/40618 ,  G06F13/1636 ,  G11C11/40603 ,  G11C11/40611

Abstract: A method of refreshing a dynamic random access memory (DRAM) includes detecting an open page of the DRAM at a row of a DRAM bank within an open sub-array of the DRAM bank. The method also includes delaying issuance of a refresh command to a target refresh row of the DRAM bank when the target refresh row of the DRAM bank is within the open sub-array of the DRAM bank.

Abstract translation: 一种刷新动态随机存取存储器（DRAM）的方法包括在DRAM存储体的开放子阵列内检测DRAM存储体的一行的DRAM的开放页面。 该方法还包括当DRAM存储体的目标刷新行位于DRAM存储体的打开子阵列内时，延迟向DRAM存储体的目标刷新行发出刷新命令。

公开(公告)号：WO2014113374A1

公开(公告)日：2014-07-24

申请号：PCT/US2014/011442

申请日：2014-01-14

Applicant: QUALCOMM INCORPORATED

Inventor： DONG, Xiangyu ,  SUH, Jungwon

IPC: G06F13/16

CPC classification number: G11C11/40603 ,  G06F12/08 ,  G06F13/1694 ,  Y02D10/14

Abstract: Heterogeneous memory systems, and related methods and computer-readable media for supporting heterogeneous memory access requests in processor-based systems are disclosed. A heterogeneous memory system is comprised of a plurality of homogeneous memories that can be accessed for a given memory access request. Each homogeneous memory has particular power and performance characteristics. In this regard, a memory access request can be advantageously routed to one of the homogeneous memories in the heterogeneous memory system based on the memory access request, and power and/or performance considerations. The heterogeneous memory access request policies may be predefined or determined dynamically based on key operational parameters, such as read/write type, frequency of page hits, and memory traffic, as non-limiting examples. In this manner, memory access request times can be optimized to be reduced without the need to make tradeoffs associated with only having one memory type available for storage.

Abstract translation: 公开了用于在基于处理器的系统中支持异构存储器访问请求的异构存储器系统以及相关方法和计算机可读介质。 异构存储器系统由可以针对给定存储器访问请求访问的多个均匀存储器组成。 每个均匀存储器具有特定的功率和性能特性。 在这方面，存储器访问请求可以有利地基于存储器访问请求以及功率和/或性能考虑路由到异构存储器系统中的同构存储器之一。 作为非限制性示例，异类存储器访问请求策略可以基于诸如读/写类型，页面命中的频率和存储器流量的关键操作参数动态地预定义或确定。 以这种方式，存储器访问请求时间可以被优化以被减少，而不需要进行与仅具有可用于存储的一个存储器类型相关联的权衡。

公开(公告)号：WO2011119645A2

公开(公告)日：2011-09-29

申请号：PCT/US2011/029481

申请日：2011-03-22

Applicant: QUALCOMM Incorporated ,  HAO, Wuyang ,  KIM, Jung Pill ,  SUH, Jungwon

Inventor： HAO, Wuyang ,  KIM, Jung Pill ,  SUH, Jungwon

IPC: G06F17/50 ,  G05F3/02 ,  G06F1/10

CPC classification number: G06F1/06 ,  H02M3/07 ,  H02M3/073 ,  H02M2003/077

Abstract: A method and apparatus for providing a clock signal to a charge pump is disclosed. In a particular embodiment, the method includes providing a first clock signal to a first charge pump unit of a charge pump. The method further includes providing a second clock signal to a second charge pump unit of the charge pump. A low-to-high transition of the first clock signal occurs substantially concurrently with a high-to-low transition of the second clock signal. Only one clock signal may be at a logic high voltage level at any given time.

Abstract translation: 公开了一种用于向电荷泵提供时钟信号的方法和装置。 在特定实施例中，该方法包括向电荷泵的第一电荷泵单元提供第一时钟信号。 该方法还包括向电荷泵的第二电荷泵单元提供第二时钟信号。 第一时钟信号的从低到高的跃迁与第二时钟信号的高到低的跃迁基本同时发生。 在任何给定时间，只有一个时钟信号可能处于逻辑高电压电平。

公开(公告)号：WO2010107772A2

公开(公告)日：2010-09-23

申请号：PCT/US2010/027450

申请日：2010-03-16

Applicant: QUALCOMM INCORPORATED ,  KANG, Woo, Tag ,  KIM, Jonghae ,  SUH, Jungwon

Inventor： KANG, Woo, Tag ,  KIM, Jonghae ,  SUH, Jungwon

IPC: H01L27/108 ,  H01L27/04

CPC classification number: H01L27/0805 ,  G06F17/5068 ,  H01L28/40 ,  Y10T29/49117

Abstract: Methods and devices of a capacitor in a semiconductor device having an increased capacitance are disclosed. In a particular embodiment, a method of forming a capacitor is disclosed. A section of a first insulating material between a first metal contact element and a second metal contact element is removed to form a channel. A second insulating material is deposited in the channel between the first metal contact element and the second metal contact element.

Abstract translation: 公开了具有增加的电容的半导体器件中的电容器的方法和装置。 在特定实施例中，公开了形成电容器的方法。 在第一金属接触元件和第二金属接触元件之间的第一绝缘材料的一部分被去除以形成通道。 在第一金属接触元件和第二金属接触元件之间的通道中沉积第二绝缘材料。

公开(公告)号：WO2019022837A1

公开(公告)日：2019-01-31

申请号：PCT/US2018/034864

申请日：2018-05-29

Applicant: QUALCOMM INCORPORATED

Inventor： CHUN, Dexter Tamio ,  SUH, Jungwon ,  LO, Michael Hawjing

IPC: G11C11/406

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/40603 ,  G11C11/40618 ,  G11C11/40626 ,  G11C11/4094

Abstract: Disclosed are techniques for minimizing performance degradation due to refresh operations in a dynamic volatile memory sub-system. In an aspect, a refresh scheduler coupled to the dynamic volatile memory sub-system generates a batch memory refresh command comprising an identification of a plurality of rows of each of one or more banks of the dynamic volatile memory sub-system to refresh, and issues the batch memory refresh command to the dynamic volatile memory sub-system.

公开(公告)号：WO2015167754A1

公开(公告)日：2015-11-05

申请号：PCT/US2015/024471

申请日：2015-04-06

Applicant: QUALCOMM INCORPORATED

Inventor： DONG, Xiangyu ,  SUH, Jungwon

IPC: G06F13/16

CPC classification number: G06F13/1642

Abstract: Priority adjustment of dynamic random access memory (DRAM) transactions prior to issuing a per-bank refresh for reducing DRAM unavailability is disclosed. In one aspect, DRAM is refreshed on a per-bank basis. If a queued memory transaction corresponds to a memory bank that will soon be refreshed, the transaction may be delayed if a refresh of the corresponding memory bank begins prior to execution of the transaction. To avoid delaying execution of the transaction while waiting for the corresponding memory bank to be refreshed, a priority of the memory transactions may be adjusted based on a memory bank refresh schedule. The priority of the transaction corresponding to the memory bank to be refreshed may be increased, and the priority of other memory transactions may be decreased, if such an adjustment would avoid or reduce delaying execution due to unavailability of the corresponding memory bank.

Abstract translation: 公开了在发布用于减少DRAM不可用性的每存储体刷新之前的动态随机存取存储器（DRAM）事务的优先级调整。 在一个方面，DRAM以每个银行为基础刷新。 如果排队的存储器事务对应于将要刷新的存储体，则如果相应的存储体的刷新在执行事务之前开始，则事务可能被延迟。 为了避免在等待相应的存储体被刷新的同时执行事务的延迟，可以基于存储体刷新调度来调整存储器事务的优先级。 可以增加与要刷新的存储体对应的事务的优先级，并且如果这样的调整将避免或减少由于对应的存储体的不可用性而导致的延迟执行，则可以减少其他存储器事务的优先级。