公开(公告)号：WO2023038790A1

公开(公告)日：2023-03-16

申请号：PCT/US2022/041200

申请日：2022-08-23

Applicant: RAMBUS INC.

Inventor： KIM, Joohee ,  LEE, Dongyun ,  WOO, Steven C.

IPC: G06F1/04 ,  G11C7/22 ,  G06F1/08

Abstract: Multiple (e.g., four) memory devices on a module are connected to a common pair of differential data strobe signal conductors. The common pair of differential data strobe conductors are also coupled to a memory controller to time the transmission of data to the multiple memory devices and to time the reception of data from the memory devices. The controller calibrates two or more different data transmission delays relative to its transmission of a write data strobe signal on the common pair of differential data strobe conductors. The controller also calibrates to account for two or more different data reception delays (skew) relative to its reception of a read data strobe signal on the common pair of differential data strobe conductors.

公开(公告)号：WO2022271581A1

公开(公告)日：2022-12-29

申请号：PCT/US2022/034142

申请日：2022-06-20

Applicant: RAMBUS INC.

Inventor： WOO, Steven, C. ,  LEE, Dongyun

IPC: G06F13/16

Abstract: A four-channel memory module includes four independent memory channels and dual channel memory devices. The channels of the dual channel memory are accessed independently. Thus, the four channels for accessing the memory module each access one channel of a first set and a second set of dual channel memory devices on the module. Dual channel data buffer devices are also included on the module. The dual channel data buffer devices also retime data strobe signals for accesses to/from the sets of dual channel memory devices.

公开(公告)号：WO2022271695A1

公开(公告)日：2022-12-29

申请号：PCT/US2022/034338

申请日：2022-06-21

Applicant: RAMBUS INC.

Inventor： WOO, Steven, C. ,  LEE, Dongyun

IPC: G06F3/06 ,  G11C5/04

Abstract: A four-channel memory module includes four independent twenty (20) data bit memory channels and dual channel memory devices. The channels of the dual channel memory are accessed independently. Thus, the four channels for accessing the memory module each access one channel of a first set and a second set of dual channel memory devices on the module. Error detection and correction codeword configurations and schemes can implement chipkill, Single symbol data correct/double symbol data detect (SSDC/DSDD). Single symbol data correct with fewer memory devices may also be implemented. Error detection and correction codeword configurations and schemes may be switched in response to detecting a failed device, signal line, or memory channel.

公开(公告)号：WO2020159800A1

公开(公告)日：2020-08-06

申请号：PCT/US2020/014853

申请日：2020-01-23

Applicant: RAMBUS INC.

Inventor： LEE, Dongyun ,  HAUKNESS, Brent, S.

IPC: G06N3/063 ,  G06F9/30 ,  G06F13/28 ,  G06F15/00 ,  G06F15/18

Abstract: An integrated-circuit neural network includes chain of multiply-accumulate units co-located with a high-bandwidth storage array. Each multiply accumulate includes a digital input port, analog input port and multiply-adder circuitry. The digital input port receives a matrix of digital-weight values from the storage array and the analog input port receives a counterpart matrix of analog input signals, each analog input signal exhibiting a respective electronic current representative of input value. The multiply-adder circuitry generates a matrix of analog output signals by convolving the matrix of digital-weight values with the matrix of analog input signals including, for each analog output signal within the matrix of analog output signals, switchably enabling weighted current contributions to the analog output signal based on logic states of on respective bits of one or more of the digital- weight values.