公开(公告)号：WO2022271581A1

公开(公告)日：2022-12-29

申请号：PCT/US2022/034142

申请日：2022-06-20

Applicant: RAMBUS INC.

Inventor： WOO, Steven, C. ,  LEE, Dongyun

IPC: G06F13/16

Abstract: A four-channel memory module includes four independent memory channels and dual channel memory devices. The channels of the dual channel memory are accessed independently. Thus, the four channels for accessing the memory module each access one channel of a first set and a second set of dual channel memory devices on the module. Dual channel data buffer devices are also included on the module. The dual channel data buffer devices also retime data strobe signals for accesses to/from the sets of dual channel memory devices.

公开(公告)号：WO2010077408A1

公开(公告)日：2010-07-08

申请号：PCT/US2009/059994

申请日：2009-10-08

Applicant: RAMBUS INC. ,  RYCHLIK, Bohuslav ,  LINSTADT, John, E. ,  HAUKNESS, Brent, S. ,  WOO, Steven, C.

Inventor： RYCHLIK, Bohuslav ,  LINSTADT, John, E. ,  HAUKNESS, Brent, S. ,  WOO, Steven, C.

IPC: G11C16/04 ,  G11C16/08

CPC classification number: G11C16/10 ,  G11C11/5628

Abstract: A method of operating a memory device includes receiving first and second sets of bits to be stored in multi-level cells in the device. A multi-level encoding is selected from among a plurality of multi-level encodings for storing the first and second sets of bits in the multi-level cells. Each multi-level encoding includes at least four encoding levels for a respective multi-level cell. Respective multi-level encodings have respective costs associated with programming the first and second sets of bits into the multi-level cells in accordance with the respective multi-level encodings. The multi-level encoding is selected based on the respective costs of the respective encodings. The first and second sets of bits are encoded in accordance with the selected multi-level encoding to produce encoded data for storage in the device such that a respective multi-level cell stores respective bits from both the first and second sets of bits.

Abstract translation: 一种操作存储器件的方法包括接收要存储在器件中的多级单元中的第一组和第二组位。 从用于存储多级单元中的第一和第二位组的多个多级编码中选择多级编码。 每个多级编码包括用于相应多级单元的至少四个编码电平。 相应的多级编码具有与根据相应的多级编码将第一和第二组位编程到多级单元中相关联的成本。 基于相应编码的相应成本来选择多级编码。 第一和第二组位根据所选择的多级编码进行编码，以产生用于存储在设备中的编码数据，使得相应的多级单元存储来自第一和第二组位的相应位。

公开(公告)号：WO2005114669A2

公开(公告)日：2005-12-01

申请号：PCT/US2005/018246

申请日：2005-05-20

Applicant: RAMBUS INC. ,  WOO, Steven, C. ,  TSANG, Brian, H.

Inventor： WOO, Steven, C. ,  TSANG, Brian, H.

IPC: G11C7/00

CPC classification number: G06F13/161 ,  G06F13/1631

Abstract: A memory system having multiple memory devices reduces average access latency by enabling different latencies for different regions of physical memory, providing an address map conducive to placing frequently accessed memory addresses into the lowest latency regions of physical memory; and assigning the frequently accessed memory addresses to the lowest latency regions of physical memory.

Abstract translation: 具有多个存储器件的存储器系统通过为不同的物理存储器区域启用不同的延迟来降低平均访问延迟，提供有助于将频繁访问的存储器地址放置到物理存储器的最低等待时间区域中的地址映射; 以及将经常访问的存储器地址分配给物理存储器的最低延迟区域。

公开(公告)号：WO2021015940A1

公开(公告)日：2021-01-28

申请号：PCT/US2020/040884

申请日：2020-07-06

Applicant: RAMBUS INC.

Inventor： KELLAM, Mark, D. ,  WOO, Steven, C. ,  VOGELSANG, Thomas ,  LINSTADT, John, Eric

IPC: G06F9/28 ,  G06F12/02 ,  G06F15/76 ,  G11C5/06 ,  H01L21/98

Abstract: An integrated circuit that includes a set of one or more logic layers that are, when the integrated circuit is stacked in an assembly with the set of stacked memory devices, electrically coupled to a set of stacked memory devices. The set of one or more logic layers include a coupled chain of processing elements. The processing elements in the coupled chain may independently compute partial results as functions of data received, store partial results, and pass partial results directly to a next processing element in the coupled chain of processing elements. The processing elements in the chains may include interfaces that allow direct access to memory banks on one or more DRAMs in the stack. These interfaces may access DRAM memory banks via TSVs that are not used for global I/O. These interfaces allow the processing elements to have more direct access to the data in the DRAM.

公开(公告)号：WO2012064670A1

公开(公告)日：2012-05-18

申请号：PCT/US2011/059644

申请日：2011-11-07

Applicant: RAMBUS INC. ,  WOO, Steven, C. ,  AMIRKHANY, Amir ,  CHEN, Catherine ,  SECKER, David ,  SHEN, Jie

Inventor： WOO, Steven, C. ,  AMIRKHANY, Amir ,  CHEN, Catherine ,  SECKER, David ,  SHEN, Jie

IPC: G06F12/00

CPC classification number: G11C7/00 ,  G06F13/1694

Abstract: One or more pins may be modally assigned to either the command/address (C/A) or data (DQ) blocks of a uniform-package, multi-modal PHY (physical signaling interface) of a memory controller, thus enabling those pins to be used as C/A pins when the PHY is connected to some memory types, and as DQ pins when the PHY is connected to other memory types.

Abstract translation: 一个或多个引脚可以被模式地分配给存储器控制器的均匀封装，多模式PHY（物理信令接口）的命令/地址（C / A）或数据（DQ）块，从而使得这些引脚 当PHY连接到某些存储器类型时，用作C / A引脚，当PHY连接到其他存储器类型时用作引脚。

公开(公告)号：WO2021133499A1

公开(公告)日：2021-07-01

申请号：PCT/US2020/061906

申请日：2020-11-24

Applicant: RAMBUS INC.

Inventor： WOO, Steven, C. ,  AGRAWAL, Amogh

IPC: G06N3/063 ,  G06N3/08 ,  G06F15/80

Abstract: An application-specific integrated circuit for an artificial neural network is integrated with a high-bandwidth memory. The neural network includes a systolic array of interconnected processing elements, including upstream processing elements and downstream processing elements. Each processing element includes input/output port pairs for concurrent forward and back propagation. The processing elements can be used for convolution, in which case the input/output port pairs can support the fast and efficient scanning of kernels relative to activations.

公开(公告)号：WO2023027984A2

公开(公告)日：2023-03-02

申请号：PCT/US2022/041028

申请日：2022-08-22

Applicant: RAMBUS INC.

Inventor： WOO, Steven, C. ,  SONG, Taeksang

IPC: G06F12/06 ,  G06F3/06 ,  G06F12/10

Abstract: The internal row addressing of each DRAM on a module is mapped such that row hammer affects different neighboring row addresses in each DRAM. Because the external row address to internal row address mapping scheme ensures that each set of neighboring rows for a given externally addressed row is different for each DRAM on the module, row hammering of a given externally addressed row spreads the row hammering errors across different externally addressed rows on each DRAM. This has the effect of confining the row hammer errors for each row that is hammered to a single DRAM per externally addressed neighboring row. By confining the row hammer errors to a single DRAM, the row hammer errors are correctible using a single device data correct (SDDC) scheme.

公开(公告)号：WO2022271695A1

公开(公告)日：2022-12-29

申请号：PCT/US2022/034338

申请日：2022-06-21

Applicant: RAMBUS INC.

Inventor： WOO, Steven, C. ,  LEE, Dongyun

IPC: G06F3/06 ,  G11C5/04

Abstract: A four-channel memory module includes four independent twenty (20) data bit memory channels and dual channel memory devices. The channels of the dual channel memory are accessed independently. Thus, the four channels for accessing the memory module each access one channel of a first set and a second set of dual channel memory devices on the module. Error detection and correction codeword configurations and schemes can implement chipkill, Single symbol data correct/double symbol data detect (SSDC/DSDD). Single symbol data correct with fewer memory devices may also be implemented. Error detection and correction codeword configurations and schemes may be switched in response to detecting a failed device, signal line, or memory channel.

公开(公告)号：WO2022060559A1

公开(公告)日：2022-03-24

申请号：PCT/US2021/048193

申请日：2021-08-30

Applicant: RAMBUS INC.

Inventor： WOO, Steven, C. ,  VOGELSANG, Thomas

IPC: H01L23/48 ,  G06F3/06

Abstract: An application-specific integrated circuit for an artificial neural network is integrated with a high-bandwidth memory. A processing die with tiled neural-network processing units is bonded to a stack of memory dies with memory banks laid out to establish relatively short connections to overlying processing units. The memory banks form vertical groups of banks for each overlying processing unit. A switch matrix on the processing die allows each processing unit to communicate with its vertical group of banks via a short, fast inter-die memory channel or with more remote groups of banks under neighboring processing units.

公开(公告)号：WO2019217118A1

公开(公告)日：2019-11-14

申请号：PCT/US2019/029591

申请日：2019-04-29

Applicant: RAMBUS INC.

Inventor： KEDIA, Amit ,  KARIYA, Kartik, Dayalal ,  MENON, Sreeja ,  WOO, Steven, C.

IPC: G06F11/07 ,  G06F11/10 ,  G06F11/30

Abstract: Multiple independent point-to-point memory channels are operated, by at least one controller, in parallel to form a wider memory channel. The memory components on these point-to-point channels include the ability to connect to multiple (e.g., 2) instances of these independent memory channels. The controller operates multiple instances of the wider channels with the memory components configured in a clamshell mode. A single memory component is also operated in clamshell mode to provide error correction code information, independently of the other wider channels, to multiple instances of the wider memory channel.