公开(公告)号：WO2003036850A1

公开(公告)日：2003-05-01

申请号：PCT/US2002/033706

申请日：2002-10-22

Applicant: RAMBUS INC.

Inventor： HAMPEL, Craig, E. ,  PEREGO, Richard, E. ,  SIDIROPOULOS, Stephanos, S. ,  TSERN, Ely, K. ,  WARE, Fredrick, A.

IPC: H04L5/16

CPC classification number: G11C11/4076 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0671 ,  G06F12/0246 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C11/40611 ,  G11C11/4072 ,  G11C11/4078 ,  G11C11/4093 ,  G11C21/00 ,  G11C2207/2254 ,  H04L7/0025 ,  H04L7/0079 ,  H04L7/0091

Abstract: Apparatus and methods are disclosed for adjusting phase of data signals to compensate for phase offset variations between devices during normal operation. The phase of data signals are adjusted individually in each transmit data unit and receive data unit across multiple data slices with a common set of phase vector clock signals and a corresponding clock cycle count signal. The transmission of signal information between a first device (such as a memory controller) (205) and a second device (such as a memory component) (210) occurs without errors even when the accumulated delays between the first device and second device change by a half symbol time interval or more during operation of the system. The apparatus reduces the circuitry required, such as phase-lock-loops (255), for individually adjusting the phase of each transmit data unit and receive data unit across multiple data slices, which in turn results in reduction in complexity and cost of the system.

Abstract translation: 公开了用于调整数据信号的相位以补偿正常操作期间设备之间的相位偏移变化的装置和方法。 数据信号的相位在每个发送数据单元中单独调整，并且通过一组公共的相位矢量时钟信号和相应的时钟周期计数信号在多个数据切片之间接收数据单元。 即使当第一设备和第二设备之间的累积延迟在半符号时间间隔期间或更长时间期间，在诸如存储器控制器205的第一设备和诸如存储器组件210的第二设备之间的信号信息的传输也不会发生错误 系统的操作。 该装置减少了所需的电路，例如锁相环255，用于单独调整每个发射数据单元的相位并在多个数据片之间接收数据单元，这又导致系统的复杂性和成本的降低。

公开(公告)号：WO2003036445A1

公开(公告)日：2003-05-01

申请号：PCT/US2002/033707

申请日：2002-10-22

Applicant: RAMBUS INC.

Inventor： HAMPEL, Craig, E. ,  PEREGO, Richard, E. ,  SIDIROPOULOS, Stephanos, S. ,  TSERN, Ely, K. ,  WARE, Fredrick, A.

IPC: G06F1/12

CPC classification number: G11C11/4076 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0671 ,  G06F12/0246 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C11/40611 ,  G11C11/4072 ,  G11C11/4078 ,  G11C11/4093 ,  G11C21/00 ,  G11C2207/2254 ,  H04L7/0025 ,  H04L7/0079 ,  H04L7/0091

Abstract: A memory system includes a memory controller (405) and a memory component (410) coupled to each other. An interface of the memory component (410) is configured to receive a first signal from the memory controller (410) with read request information, retrieve the read data information (410) from the memory core in response to the request information, and transmit to the memory controller (410) a second signal containing the read data information. The read data information includes read data symbols, where the average duration of the read data symbols, measured at the interface, defines a symbol time interval. A first external access time is measured at the interface between a first read request and read data transmitted by the interface in response to the first read request. A second external access time interval is measured at the interface between a second read request and read data transmitted by the interface in response to the second read request. The difference between the first external access time and the second external access time is greater than one-half of the symbol time interval.

Abstract translation: 存储器系统包括彼此耦合的存储器控​​制器（405）和存储器组件（410）。 存储器组件（410）的接口被配置为用读取请求信息从存储器控制器（410）接收第一信号，响应于请求信息从存储器核心检索读取的数据信息（410），并且发送到 存储器控制器（410）包含读取的数据信息的第二信号。 读数据信息包括读数据符号，其中在接口处测量的读数据符号的平均持续时间定义符号时间间隔。 在第一读取请求和由接口响应于第一读取请求而发送的读取数据之间的接口处测量第一外部访问时间。 第二外部访问时间间隔在响应于第二读取请求的第二读取请求和由接口发送的读取数据之间的接口处被测量。 第一外部访问时间和第二外部访问时间之间的差异大于符号时间间隔的一半。