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公开(公告)号：WO2022040230A1
公开(公告)日：2022-02-24
申请号：PCT/US2021/046368
申请日：2021-08-17
Applicant: SAMBANOVA SYSTEMS, INC.
Inventor： GROHOSKI, Gregory Frederick , SHAH, Manish K. , PRABHAKAR, Raghu , LUTTRELL, Mark , KUMAR, Ravinder , LEUNG, Kin Hing , CHATTERJEE, Ranen , JAIRATH, Sumti , KOEPLINGER, David Alan , SIVARAMAKRISHNAN, Ram , GRIMM, Matthew Thomas
Abstract: A data processing system comprises a pool of reconfigurable data flow resources and a runtime processor. The pool of reconfigurable data flow resources includes arrays of physical configurable units and memory. The runtime processor includes logic to receive a plurality of configuration files for user applications. The configuration files include configurations of virtual data flow resources required to execute the user applications. The runtime processor also includes logic to allocate physical configurable units and memory in the pool of reconfigurable data flow resources to the virtual data flow resources and load the configuration files to the allocated physical configurable units. The runtime processor further includes logic to execute the user applications using the allocated physical configurable units and memory.
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公开(公告)号：WO2021007131A1
公开(公告)日：2021-01-14
申请号：PCT/US2020/040832
申请日：2020-07-03
Applicant: SAMBANOVA SYSTEMS, INC.
Inventor： PRABHAKAR, Raghu , SHAH, Manish K. , NATARAJA, Pramod , JACKSON, David Brian , LEUNG, Kin Hing , SIVARAMAKRISHNAN, Ram , JAIRATH, Sumti , GROHOSKI, Gregory Frederick
Abstract: A reconfigurable data processor comprises an array of configurable units configurable to allocate a plurality of sets of configurable units in the array to implement respective execution fragments of the data processing operation. Quiesce logic is coupled to configurable units in the array, configurable to respond to a quiesce control signal to quiesce the sets of configurable units in the array on quiesce boundaries of the respective execution fragments, and to forward quiesce ready signals for the respective execution fragments when the corresponding sets of processing units are ready. An array quiesce controller distributes the quiesce control signal to configurable units in the array, and receives quiesce ready signals for the respective execution fragments from the quiesce logic.
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公开(公告)号：WO2020106769A1
公开(公告)日：2020-05-28
申请号：PCT/US2019/062289
申请日：2019-11-19
Applicant: SAMBANOVA SYSTEMS, INC.
Inventor： SHAH, Manish K. , SIVARAMAKRISHNAN, Ram , LUTTRELL, Mark , JACKSON, David Brian , PRABHAKAR, Raghu , JAIRATH, Sumti , GROHOSKI, Gregory Frederick , NATARAJA, Pramod
IPC: G06F15/78
Abstract: A reconfigurable data processor comprises a bus system, and an array of configurable units connected to the bus system, configurable units in the array including configuration data stores to store unit files comprising a plurality of sub-files of configuration data particular to the corresponding configurable units. Configurable units in the plurality of configurable units each include logic to execute a unit configuration load process, including receiving via the bus system, sub-files of a unit file particular to the configurable unit, and loading the received sub-files into the configuration store of the configurable unit. A configuration load controller connected to the bus system, including logic to execute an array configuration load process, including distributing a configuration file comprising unit files for a plurality of the configurable units in the array.
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Patent Agency Ranking
公开(公告)号：WO2022212107A1
公开(公告)日：2022-10-06
申请号：PCT/US2022/021221
申请日：2022-03-21
Applicant: SAMBANOVA SYSTEMS, INC.
Inventor： NAMA, Tejas Nagendra Babu , CHAPHEKAR, Ruddhi , SIVARAMAKRISHNAN, Ram , PRABHAKAR, Raghu , JAIRATH, Sumti , WANG, Junjue , LIANG, Kaizhao , FUCHS, Adi , MUSADDIQ, Matheen , SUJEETH, Arvind Krishna
Abstract: Disclosed is a data processing system that includes compile time logic configured to section a graph into a sequence of sections, and configure each section of the sequence of sections such that an input layer of a section processes an input, one or more intermediate layers of the corresponding section processes corresponding one or more intermediate outputs, and a final layer of the corresponding section generates a final output. The final output has a non-overlapping final tiling configuration, the one or more intermediate outputs have corresponding one or more overlapping intermediate tiling configurations, and the input has an overlapping input tiling configuration. The compile time logic is further to determine the various tiling configurations by starting from the final layer and reverse traversing through the one or more intermediate layers, and ending with the input layer.
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公开(公告)号：WO2020159775A1
公开(公告)日：2020-08-06
申请号：PCT/US2020/014652
申请日：2020-01-22
Applicant: SAMBANOVA SYSTEMS, INC.
Inventor： KOEPLINGER, David Alan , PRABHAKAR, Raghu , SIVARAMAKRISHNAN, Ram , JACKSON, David Brian , LUTTRELL, Mark
Abstract: A configurable circuit configurable according to the data width of elements of a matrix is described that includes a memory array, logic to write a matrix to the memory array having elements with a data width which can be specified using configuration data, logic for a transpose read of the matrix as-written and logic for normal read of the matrix as-written. The memory array includes first and second read ports operable in parallel. Transpose read logic and normal read logic can be coupled to the first and second read ports, respectively, allowing transpose and normal read of a matrix simultaneously.
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6.发明申请
公开(公告)号：WO2022133043A1
公开(公告)日：2022-06-23
申请号：PCT/US2021/063728
申请日：2021-12-16
Applicant: SAMBANOVA SYSTEMS, INC.
Inventor： SIVARAMAKRISHNAN, Ram , JAIRATH, Sumti , BURHAN, Emre Ali , SHAH, Manish K. , PRABHAKAR, Raghu , KUMAR, Ravinder , GOEL, Arnav , CHATTERJEE, Ranen , GROHOSKI, Gregory Frederick , LEUNG, Kin Hing , HUANG, Dawei , UNNIKRISHNAN, Manoj , RAUMANN, Martin Russell , SHAH, Bandish B.
IPC: G06F15/163 , G06F15/78
Abstract: The technology disclosed relates to runtime execution of configuration files on reconfigurable processors with varying configuration granularity. In particular, the technology disclosed relates to a runtime logic that is configured to receive a set of configuration files for an application, and load and execute a first subset of configuration files in the set of configuration files and associated application data on a first reconfigurable processor. The first reconfigurable processor has a first level of configurable granularity. The runtime logic is further configured to load and execute a second subset of configuration files in the set of configuration files and associated application data on a second reconfigurable processor. The second reconfigurable processor has a second level of configurable granularity that is different from the first level of configurable granularity.
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公开(公告)号：WO2020142623A1
公开(公告)日：2020-07-09
申请号：PCT/US2020/012079
申请日：2020-01-02
Applicant: SAMBANOVA SYSTEMS, INC
Inventor： GROHOSKI, Gregory Frederick , JAIRATH, Sumti , LUTTRELL, Mark , PRABHAKAR, Raghu , SIVARAMAKRISHNAN, Ram , SHAH, Manish K.
Abstract: A reconfigurable data processor comprises an array of configurable units and a bus system configurable to define virtual machines. The system can partition the array of configurable units into a plurality of sets of configurable units, and block communications via the bus system between configurable units within a particular set and configurable units outside the particular set. A memory access controller can be connected to the bus system, configurable to confine access to memory outside the array of configurable units originating from within the particular set to memory space allocated to the particular.
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公开(公告)号：WO2020106768A1
公开(公告)日：2020-05-28
申请号：PCT/US2019/062287
申请日：2019-11-19
Applicant: SAMBANOVA SYSTEMS, INC.
Inventor： SHAH, Manish K. , SIVARAMAKRISHNAN, Ram , LUTTRELL, Mark , JACKSON, David Brian , PRABHAKAR, Raghu , JAIRATH, Sumti , GROHOSKI, Gregory Frederick , NATARAJA, Pramod
IPC: G06F15/78
Abstract: A reconfigurable data processor comprises a bus system, and an array of configurable units connected to the bus system, configurable units in the array including configuration data stores to store unit files comprising a plurality of sub-files of configuration data particular to the corresponding configurable units. Configurable units in the plurality of configurable units each include logic to execute a unit configuration load process, including receiving via the bus system, sub-files of a unit file particular to the configurable unit, and loading the received sub-files into the configuration store of the configurable unit. A configuration load controller connected to the bus system, including logic to execute an array configuration load process, including distributing a configuration file comprising unit files for a plurality of the configurable units in the array.
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