公开(公告)号：WO2022212107A1

公开(公告)日：2022-10-06

申请号：PCT/US2022/021221

申请日：2022-03-21

Applicant: SAMBANOVA SYSTEMS, INC.

Inventor： NAMA, Tejas Nagendra Babu ,  CHAPHEKAR, Ruddhi ,  SIVARAMAKRISHNAN, Ram ,  PRABHAKAR, Raghu ,  JAIRATH, Sumti ,  WANG, Junjue ,  LIANG, Kaizhao ,  FUCHS, Adi ,  MUSADDIQ, Matheen ,  SUJEETH, Arvind Krishna

IPC: G06T1/20 ,  G06T1/60 ,  G06N3/04 ,  G06N3/08 ,  G06N3/063 ,  G06N3/0454 ,  G06N3/082 ,  G06N3/084

Abstract: Disclosed is a data processing system that includes compile time logic configured to section a graph into a sequence of sections, and configure each section of the sequence of sections such that an input layer of a section processes an input, one or more intermediate layers of the corresponding section processes corresponding one or more intermediate outputs, and a final layer of the corresponding section generates a final output. The final output has a non-overlapping final tiling configuration, the one or more intermediate outputs have corresponding one or more overlapping intermediate tiling configurations, and the input has an overlapping input tiling configuration. The compile time logic is further to determine the various tiling configurations by starting from the final layer and reverse traversing through the one or more intermediate layers, and ending with the input layer.