公开(公告)号：WO2013130318A1

公开(公告)日：2013-09-06

申请号：PCT/US2013/026874

申请日：2013-02-20

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： IGUELMAMENE, Lakhdar

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/10 ,  G11C7/1045 ,  G11C7/1057 ,  G11C7/1084

Abstract: A memory system or flash card may include a controller interface for communicating with a host. The interface utilizes multiple pre-driver logic blocks that are tolerant to different voltages. For example, one block may use gate oxide devices tolerant to IO low voltage that speed up the delay path during low voltage operation, while a second block may use gate oxide devices tolerant to IO higher voltage for backwards compatibility with devices that operate at a high IO voltage. This allows the interface to take advantage of the IO low voltage device speed for multi-purpose IO use, while still being used for both low voltage and higher voltage protocols.

Abstract translation: 存储器系统或闪存卡可以包括用于与主机通信的控制器接口。 该接口使用了多个容许不同电压的预驱动器逻辑块。 例如，一个块可以使用容忍IO低电压的栅极氧化物器件，以在低电压操作期间加速延迟路径，而第二块可以使用容许IO较高电压的栅极氧化物器件，用于与高电平工作的器件向后兼容 IO电压。 这允许接口利用IO低电压设备速度进行多用途IO使用，同时仍用于低电压和高电压协议。

公开(公告)号：WO2015102762A1

公开(公告)日：2015-07-09

申请号：PCT/US2014/066659

申请日：2014-11-20

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： IGUELMAMENE, Lakhdar

IPC: H03K3/013 ,  H03K3/3565 ,  H03K5/1252

CPC classification number: H03K3/3565 ,  H03K3/012 ,  H03K3/013 ,  H03K5/1252

Abstract: An integrated circuit ("IC") includes an input receiver with multiple hysteresis levels. An exemplary input receiver may be an input buffer with a Schmitt trigger that has multiple hysteresis windows between different high and low input voltages. This circuit may improve the input noise immunity of the external input signals and timing by allowing for a selection one of the plurality of levels depending on parameters of the input (e.g. noise level).

Abstract translation: 集成电路（“IC”）包括具有多个滞后电平的输入接收器。 示例性输入接收器可以是具有施密特特触发器的输入缓冲器，该施密特触发器在不同的高输入电压和低输入电压之间具有多个滞后窗口。 该电路可以通过根据输入的参数（例如噪声电平）允许选择多个电平中的一个来提高外部输入信号的输入噪声抗扰度和定时。

公开(公告)号：WO2011119497A1

公开(公告)日：2011-09-29

申请号：PCT/US2011/029228

申请日：2011-03-21

Applicant: SANDISK TECHNOLOGIES INC. ,  DAVIDSON, Matthew ,  HERON, Ralph ,  IGUELMAMENE, Lakhdar ,  TAL, Rony ,  DRUCK, Asher

Inventor： DAVIDSON, Matthew ,  HERON, Ralph ,  IGUELMAMENE, Lakhdar ,  TAL, Rony ,  DRUCK, Asher

IPC: G11C7/10

CPC classification number: G11C7/10 ,  G11C7/1066

Abstract: An interface for use of device whose core circuitry operates in one voltage domain, but exchanges signal with another device (or "host") according a different voltage domain, and the use of such an interface for supplying data using a double data rate (DDR) transfer, is presented. One concrete example of this situation is a memory card, where the internal circuitry uses one voltage range for its core operating voltages, but exchanges signals with a host using different, input/output voltage range. According to a general set of aspects, the interface receives data signals from the device at the device's core operating voltage domain, individually level shifts these to the input/output voltage domain, and then combines them into a DDR signal for transfer to the host device, where a (non-level shifted) clock signal from the host device is used as the select signal to form the DDR data signal.

Abstract translation: 一种使用其核心电路在一个电压域中运行但是根据不同电压域与另一个设备（或“主机”）交换信号的设备的接口，以及使用这种接口使用双倍数据速率（DDR ）转让。 这种情况的一个具体实例是存储卡，其中内部电路对其核心工作电压使用一个电压范围，但是与主机使用不同的输入/输出电压范围交换信号。 根据一般的方面，接口在设备的核心工作电压域接收来自器件的数据信号，分别将它们移动到输入/输出电压域，然后将它们组合成DDR信号以传送到主机 ，其中来自主机设备的（非电平移位）时钟信号用作选择信号以形成DDR数据信号。