中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

92 records (took 0.018 seconds)

    TECHNIQUES TO USE CHIP SELECT SIGNALS FOR A DUAL IN-LINE MEMORY MODULE
    1.
    发明申请
    TECHNIQUES TO USE CHIP SELECT SIGNALS FOR A DUAL IN-LINE MEMORY MODULE 审中-公开
    使用芯片选择信号用于双列直插存储器模块的技术

    公开(公告)号：WO2017171978A1

    公开(公告)日：2017-10-05

    申请号：PCT/US2017/013661

    申请日：2017-01-16

    Applicant: INTEL CORPORATION

    Inventor： NALE, Bill

    IPC: G06F13/38 ,  G06F9/30

    CPC classification number: G11C11/40618 ,  G11C5/04 ,  G11C7/1045 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/20

    Abstract: Examples may include techniques to use chip select signals for a dual in-line memory module (DIMM). In some examples, the chip select signals are used with either a first encoding scheme for clock enable (CKE) functionality or a second encoding scheme for on-die termination (ODT) functionality to enable memory devices on the DIMM to be accessed or controlled according to commands received with the chip select signals.

    Abstract translation: 示例可以包括将芯片选择信号用于双列直插式存储器模块（DIMM）的技术。 在一些示例中，芯片选择信号与用于时钟使能（CKE）功能的第一编码方案或用于片上终结（ODT）功能的第二编码方案一起使用，以使DIMM上的存储器设备能够被访问或根据 到与芯片选择信号一起收到的命令。

    DYNAMIC VOLTAGE ADJUSTMENT OF AN I/O INTERFACE SIGNAL
    2.
    发明申请
    DYNAMIC VOLTAGE ADJUSTMENT OF AN I/O INTERFACE SIGNAL 审中-公开
    I / O接口信号的动态电压调整

    公开(公告)号：WO2016010623A1

    公开(公告)日：2016-01-21

    申请号：PCT/US2015/031433

    申请日：2015-05-18

    Applicant: QUALCOMM INCORPORATED

    Inventor： PARK, Hee Jun ,  CHUN, Dexter, Tamio

    IPC: G11C7/10

    CPC classification number: H03K3/012 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4074 ,  G11C11/4093 ,  H03K3/011

    Abstract: Techniques for adjusting swing voltage for an I/O interface signal are described herein. In one embodiment, a device (201) comprises an input/output (I/O) interface (210), and an I/O voltage controller (205). The I/O voltage controller (205) is configured to determine a frequency or temperature of the I/O interface (210), and to adjust a swing voltage of the I/O interface based at least in part upon the determined frequency or temperature.

    Abstract translation: 本文描述了用于调整I / O接口信号的摆动电压的技术。 在一个实施例中，设备（201）包括输入/​​输出（I / O）接口（210）和I / O电压控制器（205）。 I / O电压控制器（205）被配置为确定I / O接口（210）的频率或温度，并且至少部分地基于所确定的频率或温度来调整I / O接口的摆幅电压 。

    I/O DRIVER TRANSMIT SWING CONTROL
    4.
    发明申请
    I/O DRIVER TRANSMIT SWING CONTROL 审中-公开
    I / O驱动器发送控制

    公开(公告)号：WO2014209765A1

    公开(公告)日：2014-12-31

    申请号：PCT/US2014/043285

    申请日：2014-06-19

    Applicant: INTEL CORPORATION

    Inventor： MOZAK, Christopher P. ,  TRIVEDI, Ritesh B. ,  MCCALL, James A. ,  MARTIN, Aaron

    IPC: H03K19/0175 ,  H04L25/02

    CPC classification number: H02M3/158 ,  G11C7/1057 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028 ,  G11C2207/105 ,  H04L25/0276 ,  H04L25/029

    Abstract: A transmission line interface circuit includes a voltage regulator to control a voltage swing of the transmission line interface circuit for signal transmission. The transmission line interface circuit includes complementary driver elements, including a p-type driver element to pull up the transmission line in response to a logic high, and an n-type driver element to pull down the transmission line in response to a logic low. The voltage regulator is coupled between one of the driver elements and a respective voltage reference to reduce a voltage swing of the transmission line interface circuit.

    Abstract translation: 传输线接口电路包括用于控制用于信号传输的传输线接口电路的电压摆幅的电压调节器。 传输线接口电路包括互补驱动器元件，包括响应于逻辑高来上拉传输线的p型驱动器元件，以及响应于逻辑低来拉低传输线的n型驱动器元件。 电压调节器耦合在驱动器元件之一和相应的电压基准之间，以减小传输线接口电路的电压摆幅。

    Method and Apparatus for Maintaining an Accurate I/O Calibration cell
    5.
    发明申请
    Method and Apparatus for Maintaining an Accurate I/O Calibration cell 审中-公开
    用于维持精确的I / O校准单元的方法和装置

    公开(公告)号：WO2014072769A1

    公开(公告)日：2014-05-15

    申请号：PCT/IB2012/056212

    申请日：2012-11-07

    Applicant: FREESCALE SEMICONDUCTOR, INC. ,  PRIEL, Michael ,  KUZMIN, Dan ,  SOFER, Sergey

    Inventor： PRIEL, Michael ,  KUZMIN, Dan ,  SOFER, Sergey

    IPC: G11C7/10 ,  G11C7/22

    CPC classification number: G11C7/10 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/1093 ,  G11C16/349 ,  G11C29/022 ,  G11C2207/2254

    Abstract: An integrated circuit comprising an input/output "I/O" cell (34; 36; 38; 40) arranged to drive an output signal and an activity analysis unit (24a; 24b; 24c) arranged to generate an activity factor based on the output signal. The activity factor represents a switching activity intensity of the I/O cell, the switching activity intensity is associated with an ageing effect of the I/O cell. The circuit further comprises a calibration unit (22) arranged to generate a switching pattern signal based on the generated activity factor and an I/O calibration cell (28; 30) arranged to be driven by the switching pattern signal, wherein the switching pattern signal emulates the ageing effect of the I/O cell.

    Abstract translation: 一种集成电路，包括布置成驱动输出信号的输入/输出“I / O”单元（34; 36; 38; 40）和布置成基于所述输入信号产生活动因子的活动分析单元（24a; 24b; 24c） 输出信号。 活动因子表示I / O单元的切换活动强度，开关活动强度与I / O单元的老化效应相关。 电路还包括校准单元（22），其被配置为基于所生成的活动因子产生开关模式信号，以及I / O校准单元（28; 30），被布置为由开关模式信号驱动，其中开关模式信号 模拟I / O单元的老化效果。

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：WO2013171790A1

    公开(公告)日：2013-11-21

    申请号：PCT/JP2012/003188

    申请日：2012-05-16

    Applicant: HITACHI, LTD. ,  IKEDA, Yasuhiro ,  UEMATSU, Yutaka ,  MURAOKA, Satoshi

    Inventor： IKEDA, Yasuhiro ,  UEMATSU, Yutaka ,  MURAOKA, Satoshi

    IPC: G11C7/10

    CPC classification number: G11C7/10 ,  G11C7/1057 ,  G11C7/1084

    Abstract: To suppress power consumption and enhance signal quality as compared with the case where first and second semiconductor elements are terminated only by on-chip input termination resistor circuits. A first semiconductor element with a switching function and a second semiconductor element with a switching function are connected to each other with a substrate interconnection, and a resistor element is connected in parallel with the substrate interconnection. The resistor element is placed at an arbitrary position or a branch point on the signal interconnection.

    Abstract translation: 与第一和第二半导体元件仅由片上输入终端电阻电路端接的情况相比，抑制功耗和提高信号质量。 具有开关功能的第一半导体元件和具有开关功能的第二半导体元件通过衬底互连彼此连接，并且电阻元件与衬底互连并联连接。 电阻元件放置在信号互连的任意位置或分支点处。

    POWER SAVING METHODS FOR USE IN A SYSTEM OF SERIALLY CONNECTED SEMICONDUCTOR DEVICES
    7.
    发明申请
    POWER SAVING METHODS FOR USE IN A SYSTEM OF SERIALLY CONNECTED SEMICONDUCTOR DEVICES 审中-公开
    用于串联连接半导体器件系统的节能方法

    公开(公告)号：WO2013075220A1

    公开(公告)日：2013-05-30

    申请号：PCT/CA2012/001073

    申请日：2012-11-20

    Applicant: MOSAID TECHNOLOGIES INCORPORATED

    Inventor： PYEON, Hong Beom

    IPC: G11C11/4076 ,  G11C11/4074 ,  G11C11/4093

    CPC classification number: G11C7/1057 ,  G11C5/04 ,  G11C5/147 ,  G11C7/1063 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/222 ,  G11C7/225

    Abstract: A semiconductor device comprising (i) internal circuitry for outputting at least one internal clock signal and at least one internal data/control signal for transmission to a next device in a chain of semiconductor devices; (ii) data/control output circuitry for outputting at least one output data/control signal from the at least one internal data/control signal and for releasing the at least one output data/control signal towards the next device via at least one output data/control signal line, the at least one output data/control signal having a first dynamic range; and (iii) clock output circuitry for generating at least one output clock signal from the at least one internal clock signal and for releasing the at least one output clock signal towards the next device via at least one output clock signal line, the at least one output clock signal having a dynamic range different than the first dynamic range.

    Abstract translation: 一种半导体器件，包括（i）内部电路，用于输出至少一个内部时钟信号和至少一个内部数据/控制信号，以传输到半导体器件链中的下一个器件; （ii）数据/控制输出电路，用于从所述至少一个内部数据/控制信号输出至少一个输出数据/控制信号，并且用于经由至少一个输出数据向所述下一个设备释放所述至少一个输出数据/控制信号 /控制信号线，所述至少一个输出数据/控制信号具有第一动态范围; 以及（iii）时钟输出电路，用于从所述至少一个内部时钟信号产生至少一个输出时钟信号，并且用于经由至少一个输出时钟信号线将所述至少一个输出时钟信号释放到所述下一个器件，所述至少一个 输出时钟信号具有不同于第一动态范围的动态范围。

    DRAM MEMORY INTERFACE
    8.
    发明申请
    DRAM MEMORY INTERFACE 审中-公开
    DRAM内存接口

    公开(公告)号：WO2013034650A1

    公开(公告)日：2013-03-14

    申请号：PCT/EP2012/067435

    申请日：2012-09-06

    Applicant: ST-ERICSSON SA ,  BERTHOLOM, Cedric

    Inventor： BERTHOLOM, Cedric

    IPC: G06F13/40 ,  G11C5/06 ,  G11C7/10 ,  G11C11/4093 ,  G11C7/02

    CPC classification number: G11C11/40615 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4023 ,  G11C11/4093

    Abstract: It is proposed a DRAM memory interface (40) for transmitting signals between a memory controller device (50) and a DRAM memory device (52). The DRAM memory interface comprises: data lines (44) for transmitting data signals; one or more control line(s) for transmitting control signals; one or more address line(s) for transmitting address signals; for each line, a transmitter device (41) connected to a first end of the line and a receiver device (42) connected to a second end of the line; wherein: each line is a single ended line wherein a signal transmitted on the line is referenced to a first reference voltage line (46); and - each line has an termination (Z 1 , Z 2 ) on both the first and second ends of the line by connecting a first impedance (Z 1 ) to the first end of the line and a second impedance (Z 2 ) to the second end of the line.

    Abstract translation: 提出了一种用于在存储器控制器设备（50）和DRAM存储器件（52）之间传输信号的DRAM存储器接口（40）。 DRAM存储器接口包括：用于发送数据信号的数据线（44） 用于发送控制信号的一个或多个控制线; 用于发送地址信号的一个或多个地址线; 对于每条线路，连接到线路的第一端的发射机设备（41）和连接到线路的第二端的接收机设备（42） 其中：每条线是单端线，其中在该线上发送的信号参考第一参考电压线（46）; 并且 - 每条线路通过将第一阻抗（Z1）连接到线路的第一端并且将第二阻抗（Z2）连接到线路的第二端，具有在线路的第一和第二端上的终端（Z1，Z2） 线。

    ACTIVE PULSED SCHEME FOR DRIVING LONG INTERCONNECTS
    10.
    发明申请
    ACTIVE PULSED SCHEME FOR DRIVING LONG INTERCONNECTS 审中-公开
    用于驱动长互连的主动脉冲方案

    公开(公告)号：WO2004015863A3

    公开(公告)日：2004-08-26

    申请号：PCT/US0322504

    申请日：2003-08-08

    Applicant: SUN MICROSYSTEMS INC

    Inventor： KLASS EDGARDO F ,  DEMAS ANDREW J

    IPC: G11C5/06 ,  G11C7/10 ,  H01L29/00 ,  H04L25/08

    CPC classification number: G11C7/1057 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1084

    Abstract: An interconnect structure (200) includes a signal wire (210) and an' active shield line (220) adjacent to, but removed from, signal wire (210). Interconnect structure (200) also includes another active shield line (230) adjacent to, but removed from, signal wire (210). A signal driver (205) is connected to signal wire (210). Signal driver (205) drives a pulse on signal wire (210). A shield driver (225) is connected to active shield line (220). Shield driver (220) asserts a signal on active shield line (220) substantially simultaneous with the pulse. Another shield driver (235) is connected to another active shield line (230). Another shield driver (235) asserts a signal on another active shield line (230) substantially simultaneous with the pulse. The effect of the simultaneous signals on signal wire (210) and active shield lines (220, 230) is to effectively cancel the lateral capacitances between these lines.

    Abstract translation: 互连结构（200）包括与信号线（210）相邻但从信号线（210）移除的信号线（210）和“有源屏蔽线（220）”。 互连结构（200）还包括与信号线（210）相邻但从信号线（210）移除的另一有源屏蔽线（230）。 信号驱动器（205）连接到信号线（210）。 信号驱动器（205）驱动信号线（210）上的脉冲。 屏蔽驱动器（225）连接到主动屏蔽线（220）。 屏蔽驱动器（220）基本上与脉冲同时地在主动屏蔽线（220）上断信号。 另一个屏蔽驱动器（235）连接到另一主动屏蔽线（230）。 另一屏蔽驱动器（235）基本上与脉冲同时地在另一有源屏蔽线（230）上断言信号。 信号线（210）和有源屏蔽线（220,230）上的同时信号的效果是有效地消除这些线之间的横向电容。

Patent Agency Ranking