公开(公告)号：WO2022186846A1

公开(公告)日：2022-09-09

申请号：PCT/US2021/033676

申请日：2021-05-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： LIEN, Yu-Chung ,  PAYAK, Keyur ,  TSENG, Huai-Yuan

IPC: G11C16/14 ,  G11C16/08 ,  G11C16/34 ,  G11C16/04

Abstract: Apparatuses and techniques are described for performing an erase operation for a set of memory cells, where the erase operation applies a staircase or multi-level word line voltage concurrent with a fixed level erase pulse to provide multiple channel-to-gate voltages. Current consumption and time are saved compared to applying a multi-level erase voltage to a high capacitance substrate, for example. In one approach, the word line voltage is changed from a positive erase-enable voltage to a negative erase-enable voltage during the multi-level erase pulse. A step size of a next erase pulse can be set to achieve an approximately constant step increase in channel-to-gate voltages of the memory cells.

公开(公告)号：WO2022125142A1

公开(公告)日：2022-06-16

申请号：PCT/US2021/033818

申请日：2021-05-24

Applicant: SANDISK TECHNOLOGIES LLC [US]/[US]

Inventor： LIEN, Yu-Chung ,  TSENG, Huai-Yuan ,  DUTTA, Deepanshu

IPC: G06F1/3234 ,  G11C16/10 ,  G06F3/06 ,  G11C16/30

Abstract: Apparatuses and techniques are described for reducing a peak current consumption during a program operation for a memory device. A higher current peak occurs in a first program loop of the program operation when a set of word lines is in a discharged state, also referred to as a first read condition. A current reduction countermeasure can be used when ramping up voltages of unselected word lines to a read pass voltage during the verify phase of the program loop. The countermeasure can involve reducing the ramp up rate, reducing the read pass voltage, or delaying the start of the ramp up for a portion of the word lines.

公开(公告)号：WO2021158249A1

公开(公告)日：2021-08-12

申请号：PCT/US2020/035019

申请日：2020-05-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： LIEN, Yu-Chung ,  ELIASH, Tomer ,  TSENG, Huai-Yuan

IPC: G06F3/06 ,  G11C8/08

Abstract: Apparatuses and techniques are described for managing power consumption in a memory device. When a multi -plane read command is received, a control circuit determines whether the blocks identified by the read command are fully or partially programmed. If they are fully programmed, the read command is executed while applying a common read pass voltage to the unprogrammed word lines of the respective blocks. If the blocks are not all fully programmed, the control circuit determines a last-programmed word line. If the last-programmed word lines are not equal in each block, the read command is executed while applying a base read pass voltage to the unprogrammed word lines of one or more higher-programmed blocks and a lower read pass voltage to the unprogrammed word lines of one or more lower-programmed blocks.

公开(公告)号：WO2021086439A1

公开(公告)日：2021-05-06

申请号：PCT/US2020/025567

申请日：2020-03-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： LIEN, Yu-Chung ,  TSENG, Huai-Yuan ,  DUTTA, Deepanshu ,  PRAKASH, Abhijith

IPC: G11C16/08 ,  G11C16/26 ,  G11C16/04 ,  G11C16/30 ,  G11C5/14

Abstract: Techniques are provided for operating non-volatile storage. Peak current consumption may be reduced in connection with sensing non-volatile memory cells. Peak current consumption may be reduced when a first read condition is present. In one aspect, the value of a parameter of a voltage that is applied to a word line during a pre-read phase of a sense operation is controlled in order to reduce peak current consumption when the first read condition is present. Examples of the parameter include a ramp rate, a number of intermediate voltage levels, and a start time.

公开(公告)号：WO2020263320A2

公开(公告)日：2020-12-30

申请号：PCT/US2019/066745

申请日：2019-12-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： YANG, Xiang ,  LIEN, Yu-Chung

IPC: G11C16/26 ,  G11C16/24 ,  H01L27/11582 ,  H01L27/1157 ,  G11C16/04 ,  G11C16/0483 ,  H01L27/11565

Abstract: A partial page sensing method and system are provided in which, while a bit line voltage (VBLC) is applied to first bit lines of a first partial page of a memory cell array, second bit lines, of a second partial page are floated. The second bit lines of the second partial page are bit lines which are interleaved with the first bit lines of the first partial page. Bit lines associated with one or more additional partial pages may he grounded or floated. A bit line associated with an additional partial page which is adjacent to one of the first bit lines may be floated.

公开(公告)号：WO2023022766A1

公开(公告)日：2023-02-23

申请号：PCT/US2022/027966

申请日：2022-05-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： LIEN, Yu-Chung ,  DUTTA, Deepanshu ,  YUAN, Jiahui

IPC: G11C16/24 ,  G11C16/10 ,  G11C16/04 ,  G11C16/30 ,  H01L27/11575 ,  H01L27/11582

Abstract: Apparatuses and techniques are described for controlling a bit line pre-charge voltage in a program operation based on a number of bits per cell, with a goal to reduce peak current consumption. In one aspect, the ramp up of a bit line voltage to an inhibit level is optimized according to the number of bits per cell. The ramp up can involve increasing the bit line voltage from an initial level to a target voltage at a regulated rate, then increasing the bit line voltage from the target voltage to a final voltage at an unregulated rate. In one approach, the regulated ramp rate is less for single-level cell programming compared to multi-level cell programming. The target voltage can also be optimized based on the number of bis per cell.

公开(公告)号：WO2020247023A1

公开(公告)日：2020-12-10

申请号：PCT/US2019/066823

申请日：2019-12-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： YANG, Xiang ,  LIEN, Yu-Chung

IPC: G11C16/34 ,  G11C16/08 ,  G11C8/14

Abstract: A methodology and structure for performing an erase verify in non-volatile memory is described. Both the odd wordlines and the even wordlines are driven to a high voltage level. This can be done simultaneously. The simultaneous charging of both the odd wordlines and the even wordlines, even when the erase verify will occur on only one of the odd or even wordlines reduces RC delay in the charging of the wordlines. After the odd and even wordlines are charged, then one set of wordlines, either the odd or even wordlines, is dropped to the erase verify voltage. The erase sense operation is then performed.

公开(公告)号：WO2020242534A1

公开(公告)日：2020-12-03

申请号：PCT/US2019/068679

申请日：2019-12-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： LIEN, Yu-Chung ,  YUAN, Jiahui ,  DUTTA, Deepanshu ,  PETTI, Christopher

IPC: H01L27/22 ,  H01L43/08 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  G11C11/16

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive word line layers located over a substrate, and a plurality of vertical memory strings. Each vertical memory string includes a series connection of a memory stack structure and a selector element. Each of the memory stack structures extends through the alternating stack and includes a respective memory film and a respective vertical semiconductor channel. Each of the selector elements includes a two terminal device that is configured to provide at least two different resistivity states.

公开(公告)号：WO2023069147A1

公开(公告)日：2023-04-27

申请号：PCT/US2022/028463

申请日：2022-05-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： LIEN, Yu-Chung ,  YUAN, Jiahui ,  KWON, Ohwon

IPC: G11C16/34 ,  G11C16/24 ,  G11C16/08 ,  G11C16/04 ,  H01L27/11582 ,  H01L27/11575

Abstract: A control circuit connected to non-volatile memory cells applies a programming signal to a plurality of the non-volatile memory cells in order to program the plurality of the non-volatile memory cells to a set of data states. The control circuit performs program verification for the non-volatile memory cells, including applying bit line voltages during program verification based on word line position and data state being verified.

公开(公告)号：WO2023287474A1

公开(公告)日：2023-01-19

申请号：PCT/US2022/027243

申请日：2022-05-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： LIEN, Yu-Chung ,  PRAKASH, Abhijith ,  PAYAK, Keyur ,  YUAN, Jiahui ,  TSENG, Huai-Yuan ,  YADA, Shinsuke ,  ISOZUMI, Kazuki

IPC: H01L27/11578 ,  G11C16/14 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L21/768

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, first memory opening fill structures extending through the alternating stack and including a respective first vertical semiconductor channel having a tubular section and a semi-tubular section, second memory opening fill structures, first bit lines electrically connected to a respective subset of the first drain regions, second bit lines electrically connected to a respective subset of the second drain regions, and an erase voltage application circuit configured to electrically bias the first bit lines at a first bit line erase voltage and the second bit lines at a second bit line erase voltage during an erase operation. The first bit line erase voltage is greater than the second bit line erase voltage.