公开(公告)号：WO2023022769A1

公开(公告)日：2023-02-23

申请号：PCT/US2022/028391

申请日：2022-05-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： ITOU, Ryousuke ,  SAI, Akihisa ,  IIZUKA, Kenzo

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11575

Abstract: A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate, and memory opening fill structures including vertical stacks of memory elements are formed through the vertically alternating sequence. Backside trenches are formed to divide the vertically alternating sequence into a plurality of alternating stacks of insulating layers and sacrificial material layers. Bridge structures are formed within each of the backside trenches. The sacrificial material layers are replaced with electrically conductive layers while the bridge structure are present within the backside trenches.

公开(公告)号：WO2023018499A1

公开(公告)日：2023-02-16

申请号：PCT/US2022/036456

申请日：2022-07-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： BARCLAY, M., Jared ,  HOPKINS, John, D. ,  HILL, Richard, J. ,  CHARY, Indra, V. ,  THONG, Kar, Wui

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

Abstract: A memory array comprising strings of memory cells comprises laterally- spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier by conducting material that is in a lowest of the conductive tiers and that is directly against multiple of the channel-material strings. The channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. A wall in the lowest conductive tier is aside the conducting material. The wall is in a region that is edge-of-plane relative to the memory plane. The edge-of-plane region comprises a TAV region. The wall is horizontally-elongated relative to an edge of the TAV region that is in the edge-of-plane region. Other memory arrays and methods are disclosed.

公开(公告)号：WO2022240446A1

公开(公告)日：2022-11-17

申请号：PCT/US2021/065390

申请日：2021-12-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： ZHANG, Peng ,  ZHANG, Yanli ,  YANG, Xiang ,  MATSUNO, Koichi ,  HIGASHITANI, Masaaki ,  ALSMEIER, Johann

IPC: H01L27/11582 ,  H01L21/762 ,  H01L27/11565

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory opening fill structures located within an array of memory openings vertically extending through the alternating stack, and a drain-select-level isolation structure vertically extending through drain-select-level electrically conductive layers between two rows of memory opening fill structures. The drain-select-level isolation structure may comprise a low-k dielectric material or an air gap.

公开(公告)号：WO2022225585A1

公开(公告)日：2022-10-27

申请号：PCT/US2022/012826

申请日：2022-01-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： FUJIMURA, Nobuyuki ,  SHIMIZU, Satoshi ,  MORIYAMA, Takumi

IPC: H01L27/11519 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11582

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. A plurality of arrays of memory opening fill structures is formed through the alternating stack. A plurality of dielectric plates is formed, which laterally surrounds a respective array of memory opening fill structures. Self-aligned drain-select-level isolation structures are formed between a respective neighboring pair of arrays of memory opening fill structures through gaps between neighboring pairs of the dielectric plates into a subset of layers within the alternating stack. Drain side select gate electrodes are provided from a divided subset of the spacer material layers.

公开(公告)号：WO2022111039A1

公开(公告)日：2022-06-02

申请号：PCT/CN2021/121162

申请日：2021-09-28

Applicant: 长江存储科技有限责任公司

Inventor： 许宗珂 ,  袁彬 ,  张强威 ,  许波

IPC: H01L27/115 ,  H01L27/11565

Abstract: 本公开涉及一种三维存储器及其制作方法，该三维存储器包括：栅极堆叠结构，栅极堆叠结构包括沿第一方向并列设置且直接接触的核心区和台阶区；虚拟分隔结构，在第一方向贯穿台阶区；栅极分隔结构，在第一方向贯穿核心区，栅极分隔结构具有在第一方向与虚拟分隔结构相接触的第一端部，虚拟分隔结构具有在第一方向与栅极分隔结构相接触的第二端部，且第一端部位于第二端部内。

公开(公告)号：WO2022089527A1

公开(公告)日：2022-05-05

申请号：PCT/CN2021/127009

申请日：2021-10-28

Applicant: 长江存储科技有限责任公司

Inventor： 汤召辉

IPC: H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: 本公开实施例提供了一种三维存储器及其制造方法。该方法包括以下步骤：提供半导体结构，所述半导体结构包括衬底和位于所述衬底上的堆叠结构，所述堆叠结构包括交替层叠的栅极层和介电层；或者，所述堆叠结构包括交替层叠的伪栅极层和所述介电层，其中，所述栅极层可替代所述伪栅极层；在所述堆叠结构的栅线隙区中形成凹槽，其中，所述凹槽贯穿多层所述栅极层和所述介电层；或者，所述凹槽贯穿多层所述伪栅极层和所述介电层；在所述堆叠结构表面及所述凹槽中形成绝缘层，其中，所述凹槽上方的绝缘层相对远离所述衬底的表面具有凹陷；以及对所述绝缘层进行研磨以磨平所述凹陷。

公开(公告)号：WO2022086643A1

公开(公告)日：2022-04-28

申请号：PCT/US2021/050177

申请日：2021-09-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： LUO, Shuangqiang ,  CHARY, Indra V. ,  JAIN, Harsh Narendrakumar

IPC: H01L27/11548 ,  H01L27/11551 ,  H01L27/11519 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11565

Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, a staircase structure within the stack structure having steps comprising horizontal edges of the tiers, a first insulative material vertically overlying the staircase structure, conductive contact structures comprising a conductive material extending through the first insulative material and in contact with the steps of the staircase structure, and a second insulative material extending in a first horizontal direction between horizontally neighboring conductive contact structures and exhibiting one or more different properties than the first insulative material. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：WO2022046413A1

公开(公告)日：2022-03-03

申请号：PCT/US2021/045544

申请日：2021-08-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： HOWDER, Collin ,  HOPKINS, John, D. ,  SCARBROUGH, Alyssa, N.

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11521 ,  H01L27/11519

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A lowest of the first tiers comprises conductive first sacrificial material. Conductive second material is directly electrically coupled to the conductive first sacrificial material. The conductive first sacrificial material and the conductive second material have different reduction potentials that are at least 0.5V away from one another.

公开(公告)号：WO2022046368A1

公开(公告)日：2022-03-03

申请号：PCT/US2021/044272

申请日：2021-08-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： WELLS, David H. ,  WILSON, Aaron R. ,  TESSARIOL, Paolo

IPC: H01L27/11519 ,  H01L27/11565 ,  H01L27/11521 ,  H01L27/11568

Abstract: Some embodiments include an integrated assembly having a first deck with first memory cells arranged in first tiers disposed one atop another, and having a second deck over the first deck and with second memory cells arranged in second tiers disposed one atop another. Cell- material-pillars pass through the first and second decks. The cell- material-pillars have first inter-deck inflections associated with a boundary between the first and second decks. The cell-material-pillars are arranged within a configuration which includes a first memory- block-region and a second memory-block- region. A panel is between the first and second memory-block- regions. The panel has a second inter-deck inflection associated with the boundary between the first and second decks. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：WO2022031349A1

公开(公告)日：2022-02-10

申请号：PCT/US2021/034643

申请日：2021-05-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： CUI, Zhixin ,  CHIBVONGODZE, Hardwell ,  GAUTAM, Rajdeep

IPC: G11C16/10 ,  G11C11/22 ,  G11C16/04 ,  G11C16/26 ,  G11C17/16 ,  G11C17/18 ,  H01L23/522 ,  G11C11/005 ,  G11C11/223 ,  G11C11/2273 ,  G11C11/2275 ,  G11C16/0408 ,  G11C16/0466 ,  G11C2216/26 ,  H01L23/5226 ,  H01L27/11206 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11582 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11597

Abstract: First alternating stacks of first insulating strips and first spacer material strips is formed in a first device region, second alternating stacks of second insulating strips and second spacer material strips are formed in a second device region. Each of the first line trenches is filled with a respective laterally alternating sequence of memory stack structures and first dielectric pillar structures to form a three-dimensional NAND memory. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of memory elements. Each of the second line trenches with a respective laterally alternating sequence of active region assemblies of lateral field effect transistors and second dielectric pillar structures to form a three-dimensional NOR memory. Each of the active region assemblies includes a source pillar, a drain pillar, and a tubular channel region. The spacer material strips include, or are subsequently replaced with, electrically conductive strips.