公开(公告)号：WO2021141616A1

公开(公告)日：2021-07-15

申请号：PCT/US2020/036049

申请日：2020-06-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： YANG, Seung-Yeul ,  MAKALA, Raghuveer, S. ,  ZHOU, Fei ,  RAJASHEKHAR, Adarsh ,  SHARANGPANI, Rahul

IPC: H01L27/11514 ,  H01L27/11507 ,  H01L23/528 ,  H01L27/11504 ,  H01L27/11597 ,  H01L28/40 ,  H01L29/40111 ,  H01L29/516 ,  H01L45/1233 ,  H01L45/141

Abstract: A ferroelectric tunnel junction memory device includes a bit line, a word line and a memory cell located between the bit line and the word line. The memory cell includes a ferroelectric tunneling dielectric portion and an ovonic threshold switch material portion.

公开(公告)号：WO2019005219A1

公开(公告)日：2019-01-03

申请号：PCT/US2018/019853

申请日：2018-02-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： SHIMABUKURO, Seiji ,  MAKALA, Raghuveer, S.

IPC: H01L27/11582 ,  H01L27/11575

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. A retro-stepped dielectric material portion comprising a compressive-stress-generating dielectric material on stepped surfaces of the alternating stack. Memory stack structures are formed through the first-tier alternating stack. Each of the memory stack structures includes a vertical semiconductor channel and a memory film. A patterned tensile-stress-generating material layer is formed over the retro-stepped dielectric material portion in a region that is laterally spaced outward from an outer periphery of a topmost layer within the alternating stack. The patterned tensile-stress-generating material layer applies a tensile stress to the retro-stepped dielectric material portion and to the alternating stack to compensate for the compressive stress generated by the retro-stepped dielectric material portion.

公开(公告)号：WO2021236168A1

公开(公告)日：2021-11-25

申请号：PCT/US2020/067502

申请日：2020-12-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： RAJASHEKHAR, Adarsh ,  SHARANGPANI, Rahul ,  MAKALA, Raghuveer, S. ,  ZHOU, Fei ,  ZHANG, Yanli

IPC: H01L21/822 ,  H01L21/8234 ,  H01L27/11582

Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening through the alternating stack, forming lateral recesses at levels of the sacrificial material layers around the memory opening, forming a vertical stack of discrete clam-shaped semiconductor liners in the lateral recesses, replacing the vertical stack of discrete clam-shaped semiconductor liners with a vertical stack of inner clam-shaped metallic liners, forming a vertical stack of discrete charge storage elements on the vertical sack of inner clam-shaped metallic liners, forming a tunneling dielectric layer and a vertical semiconductor channel over the vertical stack of discrete charge storage elements and the vertical stack of inner clam-shaped metallic liners, and replacing each of the sacrificial material layers with an electrically conductive layer.

公开(公告)号：WO2021154326A1

公开(公告)日：2021-08-05

申请号：PCT/US2020/035602

申请日：2020-06-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： SAID, Ramy, Nashed, Bassely ,  MAKALA, Raghuveer, S. ,  KANAKAMEDALA, Senaka ,  ZHOU, Fei ,  LEE, Yao-Sheng

IPC: H01L23/00 ,  H01L27/11524

Abstract: A bonded assembly includes a first semiconductor die containing a first substrate, first semiconductor devices, and first bonding pads that are electrically connected to a respective node of the first semiconductor devices, a second semiconductor die containing a second substrate, second semiconductor devices, and second bonding pads that are electrically connected to a respective node of the second semiconductor devices and bonded to a respective one of the first bonding pads, and at least one metal-oxide framework (MOF) dielectric layer that laterally surrounds at least one of the first bonding pads and the second bonding pads.