公开(公告)号：WO2021253572A1

公开(公告)日：2021-12-23

申请号：PCT/CN2020/104570

申请日：2020-07-24

Applicant: 珠海越亚半导体股份有限公司

Inventor： 陈先明 ,  冯磊 ,  杨威源 ,  黄本霞 ,  洪业杰

IPC: H01L23/64 ,  H01L27/13 ,  H01L28/10 ,  H01L28/40

Abstract: 本申请公开了一种电容电感嵌埋结构及其制作方法和基板，该方法包括步骤：提供金属板；在金属板上表面依次沉积第一保护层、薄膜介质层、第二保护层和上电极层，并对第一保护层、薄膜介质层、第二保护层和上电极层刻蚀形成薄膜电容及电容上电极；压合上介质层至金属板上表面，覆盖薄膜电容和电容上电极，刻蚀金属板，形成电容下电极；压合下介质层至金属板下表面，对上介质层和下介质层钻孔，形成电感通孔和电容电极通孔；电镀金属形成电感和线路层，电感设置在电感导通孔中，线路层连通电感和电容电极通孔；在上下表面沉积阻焊层，并对阻焊层光刻形成线路层电极窗口。本申请能够减薄基板厚度，实现封装小型化。

公开(公告)号：WO2021141616A1

公开(公告)日：2021-07-15

申请号：PCT/US2020/036049

申请日：2020-06-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： YANG, Seung-Yeul ,  MAKALA, Raghuveer, S. ,  ZHOU, Fei ,  RAJASHEKHAR, Adarsh ,  SHARANGPANI, Rahul

IPC: H01L27/11514 ,  H01L27/11507 ,  H01L23/528 ,  H01L27/11504 ,  H01L27/11597 ,  H01L28/40 ,  H01L29/40111 ,  H01L29/516 ,  H01L45/1233 ,  H01L45/141

Abstract: A ferroelectric tunnel junction memory device includes a bit line, a word line and a memory cell located between the bit line and the word line. The memory cell includes a ferroelectric tunneling dielectric portion and an ovonic threshold switch material portion.

公开(公告)号：WO2021133983A1

公开(公告)日：2021-07-01

申请号：PCT/US2020/066958

申请日：2020-12-23

Applicant: KEPLER COMPUTING INC.

Inventor： THAREJA, Gaurav ,  MANIPATRUNI, Sasikanth ,  DOKANIA, Rajeev Kumar ,  RAMESH, Ramamoorthy ,  MATHURIYA, Amrita

IPC: H01L27/11507 ,  H01L49/02 ,  G11C11/221 ,  H01L27/11502 ,  H01L28/40

Abstract: The memory bit-cell formed using the ferroelectric capacitor results in a taller and narrower bit-cell compared to traditional memory bit-cells. As such, more bit-cells can be packed in a die resulting in a higher density memory that can operate at lower voltages than traditional memories while providing the much sought after non- volatility behavior. The pillar capacitor includes a plug that assists in fabricating a narrow pillar.

公开(公告)号：WO2021145908A1

公开(公告)日：2021-07-22

申请号：PCT/US2020/026171

申请日：2020-04-01

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： LENG, Yaojian

IPC: H01L23/522 ,  H01L49/02 ,  H01F2027/2809 ,  H01F27/2804 ,  H01L21/707 ,  H01L23/5223 ,  H01L23/5227 ,  H01L27/016 ,  H01L28/10 ,  H01L28/40 ,  H01L28/60 ,  H03B5/12

Abstract: A system-on-chip may include an inductor-capacitor oscillator monolithically integrated into the system-on-chip The inductor-capacitor oscillator may be configured to improve frequency stability and reduce noise when compared to a resistor-capacitor oscillator. Methods of making integrated oscillators may involve forming an inductor at least partially while forming a BEOL structure on a substrate. A capacitor supported on and/or embedded within the semiconductor material of the substrate may be formed before or while forming the BEOL structure. The inductor may be connected to the capacitor in parallel at least partially utilizing the BEOL structure to form an integrated inductor-capacitor oscillator.

公开(公告)号：WO2021123015A1

公开(公告)日：2021-06-24

申请号：PCT/EP2020/086813

申请日：2020-12-17

Applicant: GRAPHCORE LIMITED

Inventor： FELIX, Stephen

IPC: H01L23/64 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/16 ,  H01L49/02 ,  H01L21/48 ,  H01L21/768 ,  H01L23/00 ,  H01L2224/0401 ,  H01L2224/05094 ,  H01L2224/13101 ,  H01L23/50 ,  H01L24/05 ,  H01L24/13 ,  H01L28/40 ,  H01L2924/00014 ,  H01L2924/1436 ,  H05K1/0215 ,  H05K1/0231 ,  H05K1/032 ,  H05K1/184 ,  H05K2201/0162

Abstract: According to a first aspect, there is provided a computer structure comprising a first silicon substrate and a second silicon substrate. Computer circuitry configured to perform computing operations is formed in the first silicon substrate, which has a self-supporting depth and an inner facing surface. A plurality of distributed capacitance units are formed in the second silicon substrate, which has an inner facing surface located in overlap with the inner facing surface of the first substrate and is connected to the first substrate via a set of connectors arranged extending depthwise of the structure between the inner facing surfaces. The inner facing surfaces have matching planar surface dimensions. The second substrate has an outer facing surface on which are arranged a plurality of connector terminals for connecting the computer structure to a supply voltage. The second substrate has a smaller depth than the first substrate.

公开(公告)号：WO2022271615A1

公开(公告)日：2022-12-29

申请号：PCT/US2022/034217

申请日：2022-06-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： SANKARAN, Swaminathan ,  SUMMERFELT, Scott, Robert ,  COOK, Benjamin

IPC: H01L21/762 ,  H01L25/065 ,  H01L25/00 ,  H01L21/0212 ,  H01L21/76224 ,  H01L21/76816 ,  H01L21/76898 ,  H01L27/013 ,  H01L28/10 ,  H01L28/40

Abstract: An integrated circuit (IC) (100) includes a semiconductor substrate (102) and an interconnect region (104). The semiconductor substrate (102) has a first surface and a second surface opposite the first surface. The semiconductor substrate (102) has a first region with a passive component (122). The semiconductor substrate has a second region outside the first region. The resistance of the second region is smaller than the resistance of the first region. The interconnection region (104) is on the second surface of the semiconductor substrate (102).

公开(公告)号：WO2021253527A1

公开(公告)日：2021-12-23

申请号：PCT/CN2020/100984

申请日：2020-07-09

Applicant: 中国科学院微电子研究所

Inventor： 罗庆 ,  姜鹏飞 ,  吕杭炳 ,  王渊 ,  刘明

IPC: H01L49/02 ,  H01L27/11502 ,  H01L28/40

Abstract: 一种HfO2基铁电电容器及其制备方法和HfO2基铁电存储器，属于微电子技术领域，通过在铁电电容的介质层和上电极（TiN）之间插入热膨胀系数小于TiN的Al2O3插层，达到增大铁电存储器存储窗口的目的。HfO2基铁电电容器，从下到上包括衬底层（1）、下电极（2）、介质层（3）、Al2O3插层（4）、上电极（5）和金属保护层（6）。可提高存储窗口大小，有效防止信息误读，从而提高存储器的可靠性。

公开(公告)号：WO2023278093A1

公开(公告)日：2023-01-05

申请号：PCT/US2022/031793

申请日：2022-06-01

Applicant: QUALCOMM INCORPORATED

Inventor： XIE, Biancun ,  PANDEY, Shree Krishna

IPC: H01L23/50 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49822 ,  H01L25/18 ,  H01L25/50 ,  H01L27/013 ,  H01L28/40

Abstract: A package that includes a substrate, an integrated device coupled to the substrate, and an integrated passive device comprising at least two capacitors. The integrated passive device is coupled to the substrate. The integrated passive device includes a passive device substrate comprising a first trench and a second trench, an oxide layer located over the first trench and the second trench, a first electrically conductive layer located over the oxide layer the first trench, a dielectric layer located over the first electrically conductive layer, and a second electrically conductive layer located over the dielectric layer.

公开(公告)号：WO2021254989A1

公开(公告)日：2021-12-23

申请号：PCT/EP2021/066028

申请日：2021-06-15

Applicant: MERCK PATENT GMBH

Inventor： NARASIMHAN, Vijay Kris ,  LEHN, Jean-Sébastien M. ,  LITTAU, Karl ,  WOODRUFF, Jacob ,  KANJOLIA, Ravindra

IPC: C23C16/40 ,  C23C16/455 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  C23C16/405 ,  C23C16/45531 ,  C23C16/45553 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/02205 ,  H01L21/0228 ,  H01L21/02304 ,  H01L28/40 ,  H01L29/516

Abstract: The disclosed and claimed subject matter relates to crystalline ferroelectric materials that include a mixture of hafnium oxide and zirconium oxide having a substantial (i.e., approximately 40% or more) or majority portion of the material in a ferroelectric phase as deposited (i.e., without the need for further processing, such as a subsequent capping or annealing) and methods for preparing and depositing these materials.

公开(公告)号：WO2021146229A1

公开(公告)日：2021-07-22

申请号：PCT/US2021/013160

申请日：2021-01-13

Applicant: CREE, INC.

Inventor： JONES, Evan ,  FISHER, Jeremy

IPC: H01L21/8252 ,  H01L27/06 ,  H01L27/07 ,  H01L49/02 ,  H01L29/20 ,  H01L27/0605 ,  H01L27/0629 ,  H01L27/0733 ,  H01L28/40 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/452 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/92

Abstract: A High Mobility Electron Transistor, HEMT, (10) and a capacitor (14, 18, 20, 22, 24) co-formed on an integrated circuit share at least one structural feature, thereby tightly integrating the two components. In one embodiment, the shared feature may be a 2DEG channel of the HEMT (10), which also functions in lieu of a base metal layer of a conventional capacitor (12). In another embodiment, a dialectic layer of the capacitor (14, 18, 20, 22, 24) may be formed in a passivation step of forming the HEMT (10). In another embodiment, a metal contact of the HEMT (10) (e.g., source, gate, or drain contact) comprises a metal layer or contact of the capacitor (22). In these embodiments, one or more processing steps required to form a conventional capacitor (12) are obviated by exploiting one or more processing steps already performed in fabrication of the HEMT (10).