公开(公告)号：WO2015117038A1

公开(公告)日：2015-08-06

申请号：PCT/US2015/013989

申请日：2015-01-30

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： WANG, Jun ,  BAIOCCHI, Frank ,  LIN, Haian

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/088 ,  H01L21/26533 ,  H01L21/761 ,  H01L21/823493 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/7816 ,  H01L29/7835 ,  H02M3/1588 ,  Y02B70/1466

Abstract: In described examples, an integrated semiconductor transistor chip (110a) for use in a buck converter includes a high side transistor (120a), which is formed on the chip (110a) and includes a laterally diffused metal oxide semiconductor (LDMOS) transistor. Also, the chip (110a) includes a low side transistor (130a), which is formed on the chip (110a) and includes a source down metal oxide semiconductor field effect transistor (MOSFET). Further, the chip (110a) includes: a substrate (138) for use as a source for the low side transistor (130a); and an n-doped well (122) for isolation of the high side transistor (120a) from the source of the low side transistor (130a).

Abstract translation: 在所述实施例中，用于降压转换器的集成半导体晶体管芯片（110a）包括形成在芯片（110a）上并包括横向扩散的金属氧化物半导体（LDMOS）晶体管的高侧晶体管（120a）。 此外，芯片（110a）包括形成在芯片（110a）上并包括源极金属氧化物半导体场效应晶体管（MOSFET）的低侧晶体管（130a）。 此外，芯片（110a）包括：用作低侧晶体管（130a）的源极的衬底（138）; 以及用于从低侧晶体管（130a）的源极隔离高侧晶体管（120a）的n掺杂阱（122）。

公开(公告)号：WO2013006703A3

公开(公告)日：2013-01-10

申请号：PCT/US2012/045560

申请日：2012-07-05

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED ,  WANG, Jun ,  XU, Shuming ,  KOREC, Jacek

Inventor： WANG, Jun ,  XU, Shuming ,  KOREC, Jacek

IPC: H01L27/02 ,  H01L29/78 ,  H01L21/336

Abstract: A power MOSFET (202) is formed in a semiconductor device (200) with a parallel combination of a shunt resistor (208) and a diode-connected MOSFET (210) between a gate input node (204) of the semiconductor device and a gate (206) of the power MOSFET. A gate (212) of the diode-connected MOSFET is connected to the gate (206) of the power MOSFET. Source and drain nodes (216, 214) of the diode-connected MOSFET are connected to a source node (218) of the power MOSFET through diodes (220). The drain node of the diode-connected MOSFET is connected to the gate input node (204) of the semiconductor device. The source node(216) of the diode-connected MOSFET is connected to the gate (206) of the power MOSFET. The power MOSFET and the diode-connected MOSFET are integrated into the substrate of the semiconductor device so that the diode- connected MOSFET source and drain nodes (216, 214) are electrically isolated from the power MOSFET source node (218) through a pn junction.