公开(公告)号：WO2016113797A1

公开(公告)日：2016-07-21

申请号：PCT/JP2015/006178

申请日：2015-12-11

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： NISHIMURA, Shinya ,  FUJIWARA, Hirokazu ,  SOEJIMA, Narumasa ,  TAKEUCHI, Yuichi

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/739

CPC classification number: H01L29/063 ,  H01L21/0465 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

Abstract: A semiconductor device includes a p-type semiconductor region in contact with a bottom face of a trench gate, wherein the p-type semiconductor region includes a first p-type semiconductor region containing a first type of p-type impurities and a second p-type semiconductor region containing a second type of p-type impurities. The first p-type semiconductor region is located between the trench gate and the second p-type semiconductor region. In a view along the depth direction, the second p-type semiconductor region is located within a part of the first p-type semiconductor region. A diffusion coefficient of the second type of p-type impurities is smaller than a diffusion coefficient of the first type of p-type impurities.

Abstract translation: 半导体器件包括与沟槽栅极的底面接触的p型半导体区域，其中p型半导体区域包括含有第一类型p型杂质的第一p型半导体区域和第二p型半导体区域， 型半导体区域包含第二类型的p型杂质。 第一p型半导体区域位于沟槽栅极和第二p型半导体区域之间。 在沿着深度方向的视图中，第二p型半导体区域位于第一p型半导体区域的一部分内。 第二类型p型杂质的扩散系数小于第一类型p型杂质的扩散系数。

公开(公告)号：WO2014060804A2

公开(公告)日：2014-04-24

申请号：PCT/IB2013/002112

申请日：2013-09-24

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  FUJIWARA, Hirokazu ,  SOEJIMA, Narumasa

Inventor： TOYOTA JIDOSHA KABUSHIKI KAISHA ,  FUJIWARA, Hirokazu ,  SOEJIMA, Narumasa

IPC: H01L21/04

CPC classification number: H01L21/0485 ,  H01L21/30604 ,  H01L21/32133

Abstract: A manufacturing method of a semiconductor device includes: forming an electric metal layer by depositing metal as art electrode material on an inside of an opening of an insulating layer on a surface of an SiC semiconductor substrate (4); widening a gap between an inner wall surface in an opening formed in the insulating layer and the electrode metal layer by etching the insulating layer after the electrode metal layer is formed; and forming, an ohmic contact between the electrode metal layer and the SiC semiconductor substrate by heating the SiC semiconductor substrate and the metal electrode layer after the insulating layer is etched.

Abstract translation: 半导体器件的制造方法包括：通过在SiC半导体衬底（4）的表面上的绝缘层的开口的内侧上沉积作为技术电极材料的金属来形成电金属层， ; 通过在形成电极金属层之后刻蚀绝缘层来扩大形成在绝缘层中的开口中的内壁表面和电极金属层之间的间隙; 以及在绝缘层被蚀刻之后，通过加热SiC半导体衬底和金属电极层，在电极金属层和SiC半导体衬底之间形成欧姆接触。