公开(公告)号：WO2016113797A1

公开(公告)日：2016-07-21

申请号：PCT/JP2015/006178

申请日：2015-12-11

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： NISHIMURA, Shinya ,  FUJIWARA, Hirokazu ,  SOEJIMA, Narumasa ,  TAKEUCHI, Yuichi

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/739

CPC classification number: H01L29/063 ,  H01L21/0465 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

Abstract: A semiconductor device includes a p-type semiconductor region in contact with a bottom face of a trench gate, wherein the p-type semiconductor region includes a first p-type semiconductor region containing a first type of p-type impurities and a second p-type semiconductor region containing a second type of p-type impurities. The first p-type semiconductor region is located between the trench gate and the second p-type semiconductor region. In a view along the depth direction, the second p-type semiconductor region is located within a part of the first p-type semiconductor region. A diffusion coefficient of the second type of p-type impurities is smaller than a diffusion coefficient of the first type of p-type impurities.

Abstract translation: 半导体器件包括与沟槽栅极的底面接触的p型半导体区域，其中p型半导体区域包括含有第一类型p型杂质的第一p型半导体区域和第二p型半导体区域， 型半导体区域包含第二类型的p型杂质。 第一p型半导体区域位于沟槽栅极和第二p型半导体区域之间。 在沿着深度方向的视图中，第二p型半导体区域位于第一p型半导体区域的一部分内。 第二类型p型杂质的扩散系数小于第一类型p型杂质的扩散系数。

公开(公告)号：WO2015044749A1

公开(公告)日：2015-04-02

申请号：PCT/IB2014/001911

申请日：2014-09-24

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： SOENO, Akitaka ,  ONOGI, Atsushi ,  MIZUNO, Shoji ,  TAKEUCHI, Yuichi ,  SHOJI, Tomoyuki ,  WATANABE, Yukihiko

IPC: H01L21/308 ,  H01L29/66

CPC classification number: H01L21/3083 ,  H01L21/3085 ,  H01L21/3088 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: An oxide film (24) is formed on a surface of a semiconductor substrate (2). A resist layer (26) is formed on a surface of the oxide film. The resist layer has an opening (26a). A tapered trench (24a) is formed by forming wall surfaces (24b) of the oxide film by etching a part of the oxide film exposed from the opening. The wall surfaces are inclined with respect to a direction perpendicular to the surface of the semiconductor substrate and reach the surface of the semiconductor substrate. A space between the wall surfaces is narrowed towards the surface of the semiconductor substrate. The semiconductor substrate is etched through the tapered trench. A width of the tapered trench formed on the surface of the semiconductor substrate is smaller than a width of the opening formed in the resist layer.

Abstract translation: 在半导体衬底（2）的表面上形成氧化膜（24）。 在氧化物膜的表面上形成抗蚀剂层（26）。 抗蚀剂层具有开口（26a）。 通过蚀刻从开口暴露的氧化膜的一部分，形成氧化物膜的壁表面（24b）形成锥形沟槽（24a）。 壁面相对于与半导体衬底的表面垂直的方向倾斜并到达半导体衬底的表面。 壁表面之间的空间朝向半导体衬底的表面变窄。 通过锥形沟槽蚀刻半导体衬底。 形成在半导体衬底的表面上的锥形沟槽的宽度小于在抗蚀剂层中形成的开口的宽度。