公开(公告)号：WO2011156038A3

公开(公告)日：2012-01-26

申请号：PCT/US2011028805

申请日：2011-03-17

Applicant: UNIV VIRGINIA PATENT FOUND ,  CALHOUN BENTON H ,  RYAN JOSEPH F

Inventor： CALHOUN BENTON H ,  RYAN JOSEPH F

IPC: H03K19/00

CPC classification number: H03K19/17744 ,  H03K19/17784 ,  H03K19/17788

Abstract: A sub-VT FPGA uses a low swing, dual-VDD interconnect scheme to reduce FPGA area per LUT, delay at a constant energy, and energy at a constant delay relative to a conventional design at low voltage. These improvements are made possible by a custom asynchronous sense amp, a separated voltage for memory cells, and an improved passgate interconnect to optimize routing delay with low energy overhead. This sub-threshold FPGA design enables energy efficient and cost effective configurable logic for a wide variety of ULP applications.

Abstract translation: 子VT FPGA采用低摆幅双VDD互连方案，以降低每个LUT的FPGA面积，以恒定能量延迟，而在低电压下相对于传统设计，能够以恒定的延迟。 这些改进可以通过定制的异步感测放大器，用于存储器单元的分离电压以及改进的通道互连来实现，以优化具有低能量开销的路由延迟。 该子阈值FPGA设计可为各种ULP应用提供高能效且具有成本效益的可配置逻辑。