公开(公告)号：WO2016028769A1

公开(公告)日：2016-02-25

申请号：PCT/US2015/045677

申请日：2015-08-18

Applicant: CUMMINS, INC.

Inventor： MEYER, William D. ,  VAIDYA, Meenal R. ,  VENUGOPAL, Rishvanth Kora

IPC: F02D41/20

CPC classification number: F02M51/005 ,  F02D41/20 ,  F02D41/2096 ,  F02D2041/2003 ,  F02D2041/2072 ,  H03K19/17788

Abstract: A fuel system includes an electronic control module (ECM), at least one injector coupled to the ECM, and a configurable output driver circuit coupled to the at least one injector. The configurable output driver circuit includes a channel that enables adaptation of ECM outputs. The configurable output driver circuit is configurable based on a value stored in a register circuit.

Abstract translation: 燃料系统包括电子控制模块（ECM），耦合到ECM的至少一个喷射器以及耦合到所述至少一个喷射器的可配置输出驱动器电路。 可配置的输出驱动器电路包括一个能够调整ECM输出的通道。 可配置的输出驱动器电路可以基于存储在寄存器电路中的值来配置。

公开(公告)号：WO2017011479A1

公开(公告)日：2017-01-19

申请号：PCT/US2016/041942

申请日：2016-07-12

Applicant: XILINX, INC.

Inventor： KIREEV, Vassili ,  LIAO, Yu

IPC: H03K5/24 ,  H03K19/094 ,  H03K19/177 ,  H04L25/49

CPC classification number: H04L25/4919 ,  H03K5/2481 ,  H03K19/09425 ,  H03K19/17788 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/4917

Abstract: A circuit for generating a modulated signal in a transmitter of an integrated circuit is disclosed. The circuit comprises a transmitter driver circuit (302) having a first current path (325) for receiving a first input signal (Dataln) of a pair of differential input signals and a second current path (329) for receiving a second input signal (Dataln_b) of the pair of differential input signals, the transmitter driver circuit comprising a tail current path (327) coupled to each of the first current path and the second current path; a first current source (370) coupled between a first reference voltage (AVCCAUX) and ground (AVSS), wherein a first current of the first current source is proportional to the tail current of the tail current path; a first pull-up current source (460) coupled between the first reference voltage and a first output node (314) of the transmitter driver circuit; and a second pull-up current source (480) coupled between the first reference voltage and a second output node (320) of the transmitter driver circuit. A method of generating a modulated signal in a transmitter of an integrated circuit is also disclosed.

Abstract translation: 公开了一种用于在集成电路的发射机中产生调制信号的电路。 该电路包括具有用于接收一对差分输入信号的第一输入信号（Dataln）和用于接收第二输入信号（Dataln_b）的第二电流路径（329））的第一电流路径（325）的发射器驱动电路（302） ）所述一对差分输入信号，所述发射器驱动器电路包括耦合到所述第一电流路径和所述第二电流路径中的每一个的尾电流路径（327） 耦合在第一参考电压（AVCCAUX）和地（AVSS）之间的第一电流源（370），其中第一电流源的第一电流与尾电流路径的尾电流成比例; 第一上拉电流源（460），耦合在所述第一参考电压和所述发射器驱动器电路的第一输出节点（314）之间; 以及耦合在所述发射器驱动器电路的所述第一参考电压和第二输出节点（320）之间的第二上拉电流源（480）。 还公开了一种在集成电路的发射机中产生调制信号的方法。

公开(公告)号：WO2015030877A1

公开(公告)日：2015-03-05

申请号：PCT/US2014/033527

申请日：2014-04-09

Applicant: XILINX, INC.

Inventor： SEWANI, Aman ,  UPADHYAYA, Parag

IPC: H03K19/177

CPC classification number: H03K19/018521 ,  H03K19/17744 ,  H03K19/1778 ,  H03K19/17788

Abstract: An input/output circuit (102) implemented in an integrated circuit (100) is described. The input/output circuit comprises an input/output pad (202, 204) and a voltage control circuit (229) coupled to the input/output pad. The voltage control circuit sets a voltage at the input/output pad at a first voltage when the input/output pad is implemented as an input pad (RX Mode control: high) and at a second voltage when the input/output pad is implemented as an output pad (RX Mode Control: low). Methods of implementing input/output circuits in an integrated circuit are also described.

Abstract translation: 描述了在集成电路（100）中实现的输入/输出电路（102）。 输入/输出电路包括耦合到输入/输出焊盘的输入/输出焊盘（202,204）和电压控制电路（229）。 当输入/输出焊盘实现为输入焊盘（RX模式控制：高）时，电压控制电路以第一电压设置输入/输出焊盘处的电压，并且当输入/输出焊盘实现为 输出板（RX模式控制：低）。 还描述了在集成电路中实现输入/输出电路的方法。

公开(公告)号：WO2011156038A3

公开(公告)日：2012-01-26

申请号：PCT/US2011028805

申请日：2011-03-17

Applicant: UNIV VIRGINIA PATENT FOUND ,  CALHOUN BENTON H ,  RYAN JOSEPH F

Inventor： CALHOUN BENTON H ,  RYAN JOSEPH F

IPC: H03K19/00

CPC classification number: H03K19/17744 ,  H03K19/17784 ,  H03K19/17788

Abstract: A sub-VT FPGA uses a low swing, dual-VDD interconnect scheme to reduce FPGA area per LUT, delay at a constant energy, and energy at a constant delay relative to a conventional design at low voltage. These improvements are made possible by a custom asynchronous sense amp, a separated voltage for memory cells, and an improved passgate interconnect to optimize routing delay with low energy overhead. This sub-threshold FPGA design enables energy efficient and cost effective configurable logic for a wide variety of ULP applications.

Abstract translation: 子VT FPGA采用低摆幅双VDD互连方案，以降低每个LUT的FPGA面积，以恒定能量延迟，而在低电压下相对于传统设计，能够以恒定的延迟。 这些改进可以通过定制的异步感测放大器，用于存储器单元的分离电压以及改进的通道互连来实现，以优化具有低能量开销的路由延迟。 该子阈值FPGA设计可为各种ULP应用提供高能效且具有成本效益的可配置逻辑。

公开(公告)号：WO2010043838A2

公开(公告)日：2010-04-22

申请号：PCT/GB2009002041

申请日：2009-08-20

Applicant: ADVANCED RISC MACH LTD ,  HILL STEPHEN JOHN ,  MULLER MICHAEL PETER

Inventor： HILL STEPHEN JOHN ,  MULLER MICHAEL PETER

IPC: G06F1/32 ,  H03K19/00

CPC classification number: H03K19/17772 ,  H03K19/17784 ,  H03K19/17788

Abstract: An integrated circuit (8) comprising an array (10) of interconnected configurable logic elements (12), such as an FPGA array, is provided. The logic elements are used to form a power controller (14) which separately controls the power state of different regions of the array. Each region of the array contains one or more logic elements. Each region has a corresponding region controller (16) responsive to one or more power signals generated by the power controller to switch that region into the requested power state.

Abstract translation: 提供了包括诸如FPGA阵列的互连的可配置逻辑元件（12）的阵列（10）的集成电路（8）。 逻辑元件用于形成分别控制阵列的不同区域的功率状态的功率控制器（14）。 数组的每个区域都包含一个或多个逻辑元素。 每个区域具有响应于由功率控制器产生的一个或多个功率信号以将该区域切换到所请求的功率状态的对应的区域控制器（16）。

公开(公告)号：WO2015002681A1

公开(公告)日：2015-01-08

申请号：PCT/US2014/033526

申请日：2014-04-09

Applicant: XILINX, INC.

Inventor： CAMAROTA, Rafael, C.

IPC: H03K19/177 ,  G01R31/3185 ,  G01R31/317

CPC classification number: G01R31/26 ,  G01R31/31721 ,  G01R31/31723 ,  G01R31/318505 ,  G01R31/318516 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/17772 ,  H03K19/17788

Abstract: An apparatus for a monolithic integrated circuit die (200) is disclosed. In this apparatus, the monolithic integrated circuit die (200) has a plurality of modular die regions (211, 212). The modular die regions (211, 212) respectively have a plurality of power distribution networks (271, 272) for independently powering each of the modular die regions. Each adjacent pair of the modular die regions (211, 212) is stitched together with a respective plurality of metal lines (260, 301 -304, 514, 524).

Abstract translation: 公开了一种用于单片集成电路管芯（200）的装置。 在该装置中，单体集成电路管芯（200）具有多个模块管芯区域（211,212）。 模块化管芯区域（211,212）分别具有用于独立地为每个模块管芯区域供电的多个配电网络（271,272）。 每个相邻的一对模块模具区域（211,212）与相应的多个金属线（260,301,304,514,524）缝合在一起。

公开(公告)号：WO2011156038A2

公开(公告)日：2011-12-15

申请号：PCT/US2011/028805

申请日：2011-03-17

Applicant: UNIVERSITY OF VIRGINIA PATENT FOUNDATION ,  CALHOUN, Benton, H. ,  RYAN, Joseph, F.

Inventor： CALHOUN, Benton, H. ,  RYAN, Joseph, F.

IPC: H01L25/16

CPC classification number: H03K19/17744 ,  H03K19/17784 ,  H03K19/17788

Abstract: A sub-V T FPGA uses a low swing, dual-V DD interconnect scheme to reduce FPGA area per LUT, delay at a constant energy, and energy at a constant delay relative to a conventional design at low voltage. These improvements are made possible by a custom asynchronous sense amp, a separated voltage for memory cells, and an improved passgate interconnect to optimize routing delay with low energy overhead. This sub-threshold FPGA design enables energy efficient and cost effective configurable logic for a wide variety of ULP applications.

Abstract translation: 子VT FPGA采用低摆幅双VDD互连方案，以降低每个LUT的FPGA面积，以恒定能量延迟，而在低电压下相对于传统设计，能够以恒定的延迟。 这些改进可以通过定制的异步感测放大器，用于存储器单元的分离电压以及改进的通道互连来实现，以优化具有低能量开销的路由延迟。 该子阈值FPGA设计可为各种ULP应用提供高能效且具有成本效益的可配置逻辑。