公开(公告)号：WO2017176381A2

公开(公告)日：2017-10-12

申请号：PCT/US2017/018925

申请日：2017-02-22

Applicant: UNIVERSITY OF SOUTH FLORIDA

Inventor： IYENGAR, Anirudh, Srikant ,  GHOSH, Swaroop ,  VONTELA, Deepakreddy ,  NIRMALA, Ithihasareddy

IPC: H01L29/80

Abstract: Disclosed are various embodiments providing circuitry that includes camouflaged gates that each have multiple switches arranged in a predefined format. A switch at a specific position in one camouflaged gate can have a different threshold voltage than a switch at the specific position in another camouflaged gate. The logical function performed by the camouflaged gate can be based on which of the switches have a low threshold voltage and which of the switches have a high threshold voltage.

公开(公告)号：WO2015171620A1

公开(公告)日：2015-11-12

申请号：PCT/US2015/029255

申请日：2015-05-05

Applicant: UNIVERSITY OF SOUTH FLORIDA ,  GHOSH, Swaroop ,  IYENGAR, Anirudh Srikant ,  RAMCLAM, Kenneth

Inventor： GHOSH, Swaroop ,  IYENGAR, Anirudh Srikant ,  RAMCLAM, Kenneth

IPC: G11C11/16

CPC classification number: G11C19/0866 ,  B82Y10/00 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C19/0841 ,  G11C19/0875

Abstract: A system and method for providing a physically unclonable function (PFU) is described. In operation, the method includes applying a domain wall shift pulse challenge to a plurality of nanowires of a domain wall memory (DWM) array, wherein the nanowires of the domain wall memory (DWM) array have process induced variations, resulting in pinning potentials which affect the velocity of the domain walls along the length of the nanowires. Following the application of the domain wall shift pulse, the response to the challenge is determined by measuring the response of the plurality of nanowires of the domain wall memory to the applied domain wall shift pulse challenge to provide a physically unclonable function (PUF) for the integrated circuit.

Abstract translation: 描述了用于提供物理不可克隆功能（PFU）的系统和方法。 在操作中，该方法包括对域壁存储器（DWM）阵列的多个纳米线应用域壁移位脉冲挑战，其中域壁存储器（DWM）阵列的纳米线具有处理引起的变化，导致固定电位， 影响沿着纳米线长度的畴壁的速度。 在应用域壁移位脉冲之后，通过测量域壁存储器的多个纳米线对所应用的域壁移位脉冲挑战的响应来确定对挑战的响应，以提供用于所述域壁移位脉冲的物理不可克隆功能（PUF） 集成电路。

公开(公告)号：WO2017176381A3

公开(公告)日：2017-10-12

申请号：PCT/US2017/018925

申请日：2017-02-22

Applicant: UNIVERSITY OF SOUTH FLORIDA

Inventor： IYENGAR, Anirudh, Srikant ,  GHOSH, Swaroop ,  VONTELA, Deepakreddy ,  NIRMALA, Ithihasareddy

IPC: H03K19/173

Abstract: Disclosed are various embodiments providing circuitry that includes camouflaged gates that each have multiple switches arranged in a predefined format. A switch at a specific position in one camouflaged gate can have a different threshold voltage than a switch at the specific position in another camouflaged gate. The logical function performed by the camouflaged gate can be based on which of the switches have a low threshold voltage and which of the switches have a high threshold voltage.

Abstract translation: 公开了提供包括伪装栅极的电路的各种实施例，每个伪装栅极具有以预定格式排列的多个开关。 在一个伪装门中的特定位置处的开关可以具有与在另一个伪装门中的特定位置处的开关不同的阈值电压。 由伪装门执行的逻辑功能可以基于哪个开关具有低阈值电压以及哪个开关具有高阈值电压。