公开(公告)号：WO2021194787A1

公开(公告)日：2021-09-30

申请号：PCT/US2021/022399

申请日：2021-03-15

Applicant: XILINX, INC.

Inventor： MORSHED, Abbas ,  ARBEL, Ygal ,  KIM, Eun Mi

IPC: G06F15/78 ,  H04L12/933 ,  G06F13/14 ,  G06F13/4027 ,  G06F15/7825 ,  G06F2205/064 ,  G06F2213/0038 ,  G06F5/10 ,  G06F9/38 ,  H04L49/15 ,  H04L49/355

Abstract: Embodiments herein describe a SoC that includes a NoC that supports both strict and relax ordering requests. That is, some applications may require strict ordering where requests transmitted from the same ingress logic to different egress logic blocks are performed sequentially. However, other applications may not require strict ordering, such as interleaved writes to memory. In those applications, relax ordering can be used were the same ingress logic block can transmit multiple requests to different egress logic blocks in parallel. For example, an ingress logic block may receive a first request that is indicated as being a relaxed ordered request. After transmitting the request to an egress logic block, the ingress logic block may receive a second request. The ingress logic block can transmit the second request to a different egress logic block without waiting for a response for the first request.

公开(公告)号：WO2020018810A1

公开(公告)日：2020-01-23

申请号：PCT/US2019/042430

申请日：2019-07-18

Applicant: XILINX, INC.

Inventor： SWARBRICK, Ian A. ,  AHMAD, Sagheer ,  ARBEL, Ygal ,  GAITONDE, Dinesh D.

IPC: G06F13/16 ,  H04L12/933 ,  G06F15/78 ,  H04L12/927 ,  G06F13/40 ,  G06F21/76 ,  H04L12/24

Abstract: An example programmable integrated circuit, IC, includes a processor, a plurality of endpoint circuits, a network-on-chip, NoC (106), having NoC master units, NMUs (202), NoC slave units, NSUs (204), NoC programmable switches, NPSs (206), a plurality of registers (212), and a NoC programming interface, NPI (210). The processor is coupled to the NPI and is configured to program the NPSs by loading an image to the registers through the NPI for providing physical channels between NMUs to the NSUs and providing data paths between the plurality of endpoint circuits.

公开(公告)号：WO2019246534A1

公开(公告)日：2019-12-26

申请号：PCT/US2019/038490

申请日：2019-06-21

Applicant: XILINX, INC

Inventor： ARBEL, Ygal ,  AHMAD, Sagheer ,  SINGH, Gaurav

IPC: G06F12/1027

Abstract: An example programmable integrated circuit (IC) includes a processing system (2) having a processor (5), a master circuit (404), and a system memory management unit (SMMU) (80). The SMMU includes a first translation buffer unit (TBU) (410) coupled to the master circuit, an address translation (AT) circuit (412), an AT interface (414) coupled to the AT circuit, and a second TBU (411) coupled to the AT circuit, and programmable logic (3) coupled to the AT circuit in the SMMU through the AT interface.

公开(公告)号：WO2019032740A1

公开(公告)日：2019-02-14

申请号：PCT/US2018/045865

申请日：2018-08-08

Applicant: XILINX, INC.

Inventor： ARBEL, Ygal

IPC: G06F11/34 ,  G06F13/16 ,  G06F11/30

Abstract: Disclosed approaches of controlling quality of service in servicing memory transactions includes periodically reading (206) by a quality of service management (QM) circuit (1 16), respective first data rate metrics and respective latency metrics from requester circuits (106, 108, 1 10, 1 12) while the requester circuits are actively transmitting memory transactions to a memory controller (104). The QM circuit periodically reads (208) a second data rate metric from the memory controller while the memory controller is processing the memory transactions, and determines (210), while the requester circuits are actively transmitting memory transactions to the memory controller, whether or not the respective first data rate metrics, respective latency metrics, and second data rate metric satisfy a quality of service metric. In response to determining that the operating metrics do not satisfy the quality of service metric, the QM circuit dynamically changes (212) value(s) of a control parameter(s) of the requester circuit(s) and of the memory controller.

公开(公告)号：WO2015191474A1

公开(公告)日：2015-12-17

申请号：PCT/US2015/034739

申请日：2015-06-08

Applicant: XILINX, INC.

Inventor： ARBEL, Ygal ,  MURRAY, James, J. ,  KWON, Hyun, W. ,  PATEL, Nishit

IPC: G06F13/28

CPC classification number: G06F12/145 ,  G06F13/00 ,  G06F13/28 ,  G06F13/30

Abstract: A circuit for enabling access to data is described. The circuit comprises a memory device (104) storing data blocks having a first predetermined size; and a direct memory access circuit (195) coupled to the memory device, the direct memory circuit accessing a data payload having a second predetermined size which is greater than the first predetermined size; wherein the direct memory access circuit accesses the data payload in response to a descriptor having a plurality of addresses corresponding to a predetermined number of the data blocks stored in the memory device. A method of enabling the access to data is also disclosed.

Abstract translation: 描述了一种能够访问数据的电路。 该电路包括存储具有第一预定大小的数据块的存储器件（104） 以及耦合到所述存储器件的直接存储器访问电路（195），所述直接存储器电路访问具有大于所述第一预定大小的第二预定尺寸的数据有效载荷; 其中所述直接存储器访问电路响应于具有对应于存储在所述存储器件中的预定数量的数据块的多个地址的描述符来访问所述数据有效载荷。 还公开了一种能够访问数据的方法。

公开(公告)号：WO2023033887A1

公开(公告)日：2023-03-09

申请号：PCT/US2022/031208

申请日：2022-05-26

Applicant: XILINX, INC.

Inventor： SRINIVASAN, Krishnan ,  AHMAD, Sagheer ,  ARBEL, Ygal

IPC: G06F13/38 ,  H04L49/9057 ,  G06F13/40 ,  H04L47/36 ,  H04L49/00 ,  H04L67/565 ,  H04L25/14 ,  G06F13/42

Abstract: Embodiments herein describe on-demand packetization where data (115) that is too large to be converted directly into data words (DWs) (130) for a chip-to-chip (C2C) interface (140) are packetized instead. When identifying a protocol word (115) that is larger than the DW (130) of the C2C interface (140), a protocol layer (120a) can perform packetization where a plurality of protocol words (115) are packetized and sent as a transfer. In one embodiment, the protocol layer (120a) removes some or all of the control data or signals in the protocol words (120a) so that the protocol words no longer exceed the size of the DW (130). These shortened protocol words (115) can then be mapped to DWs (130) and transmitted as separate packets on the C2C (140). The protocol layer (120a) can then collect the portion of the control data that was removed from the protocol words (115) and transmit this data as a separate packet on the C2C interface (140).

公开(公告)号：WO2020023937A1

公开(公告)日：2020-01-30

申请号：PCT/US2019/043800

申请日：2019-07-26

Applicant: XILINX, INC.

Inventor： ARBEL, Ygal ,  AHMAD, Sagheer ,  JAYADEV, Balakrishna

IPC: G06F13/42 ,  H04L12/801 ,  G06F13/38 ,  G06F13/40 ,  G11C5/02 ,  G11C7/10

Abstract: Techniques related to a high bandwidth interface (HBI) (206) for communication between multiple host devices (202, 204) on an interposer (200) are described. In an example, the HBI (206) repurposes a portion of the high bandwidth memory (HBM) interface, such as the physical layer (402). A computing system is provided. The computing system includes a first host device (202) and at least a second host device (204). The first host device (202) is a first die on an interposer (200) and the second host device (204) is a second die on the interposer (200). The first host device (202) and the second host device (204) are interconnected via at least one HBI (206). The HBI (206) implements a layered protocol (402, 404, 406) for communication between the first host device (202) and the second host device (204). The layered protocol (402, 404, 406) includes a physical layer protocol (402) that is configured according to a HBM physical layer protocol.

公开(公告)号：WO2019152716A1

公开(公告)日：2019-08-08

申请号：PCT/US2019/016158

申请日：2019-01-31

Applicant: XILINX, INC.

Inventor： SWARBRICK, Ian, A. ,  ARBEL, Ygal ,  MITTAL, Millind ,  AHMAD, Sagheer

IPC: H04L12/933 ,  G06F15/78 ,  H04L12/701 ,  H04L29/08 ,  H04W4/50

Abstract: An example method of generating a configuration for a network on chip (NoC) in a programmable device includes: receiving (502) traffic flow requirements for a plurality of traffic flows; assigning (508) routes through the NoC for each traffic flow based on the traffic flow requirements; determining (514) arbitration settings for the traffic flows along the assigned routes; generating (516) programming data for the NoC; and loading (518) the programming data to the programmable device to configure the NoC.

公开(公告)号：WO2019160988A1

公开(公告)日：2019-08-22

申请号：PCT/US2019/017896

申请日：2019-02-13

Applicant: XILINX, INC.

Inventor： ARBEL, Ygal ,  SWARBRICK, Ian A. ,  AHMAD, Sagheer

IPC: G06F1/3287

Abstract: Examples of the present disclosure generally relate to integrated circuits, such as a system-on-chip (SoC), that include a memory subsystem. In some examples, an integrated circuit (100) includes a first master circuit (102) in a first power domain (202) on a chip; a second master circuit (104) in a second power domain (204) on the chip; and a first memory controller (1 10) in a third power domain (206) on the chip. The first master circuit (102) and the second master circuit (104) each are configured to access memory (124) via the first memory controller (1 10). The first power domain (202) and the second power domain (204) each are separate and independent from the third power domain (206).

公开(公告)号：WO2019125584A1

公开(公告)日：2019-06-27

申请号：PCT/US2018/055068

申请日：2018-10-09

Applicant: XILINX, INC.

Inventor： ARBEL, Ygal ,  SWARBRICK, Ian, A. ,  AHMAD, Sagheer

IPC: G06F11/10

Abstract: An example integrated circuit (IC) includes a network-on-chip (NoC) (106), a master device (302) coupled to the NoC, a memory controller (304) coupled to the NoC configured to control a memory coupled to the IC, and an inline error-correcting code (ECC) circuit (112) coupled to the NoC. The ECC circuit is configured to receive read and write transactions from the master device that target the memory, compute ECC data based on the read and write transactions, and provide outgoing transactions to the memory controller.