公开(公告)号：WO2023033887A1

公开(公告)日：2023-03-09

申请号：PCT/US2022/031208

申请日：2022-05-26

Applicant: XILINX, INC.

Inventor： SRINIVASAN, Krishnan ,  AHMAD, Sagheer ,  ARBEL, Ygal

IPC: G06F13/38 ,  H04L49/9057 ,  G06F13/40 ,  H04L47/36 ,  H04L49/00 ,  H04L67/565 ,  H04L25/14 ,  G06F13/42

Abstract: Embodiments herein describe on-demand packetization where data (115) that is too large to be converted directly into data words (DWs) (130) for a chip-to-chip (C2C) interface (140) are packetized instead. When identifying a protocol word (115) that is larger than the DW (130) of the C2C interface (140), a protocol layer (120a) can perform packetization where a plurality of protocol words (115) are packetized and sent as a transfer. In one embodiment, the protocol layer (120a) removes some or all of the control data or signals in the protocol words (120a) so that the protocol words no longer exceed the size of the DW (130). These shortened protocol words (115) can then be mapped to DWs (130) and transmitted as separate packets on the C2C (140). The protocol layer (120a) can then collect the portion of the control data that was removed from the protocol words (115) and transmit this data as a separate packet on the C2C interface (140).

公开(公告)号：WO2023027791A1

公开(公告)日：2023-03-02

申请号：PCT/US2022/030787

申请日：2022-05-24

Applicant: XILINX, INC.

Inventor： SRINIVASAN, Krishnan ,  AHMAD, Sagheer

IPC: H04L25/49

Abstract: Transmitter circuitry includes inversion circuitry, first transform circuitry, and selection circuitry. The inversion circuitry generates a first transformed data word by inverting one or more of a plurality of bits of a first data word. The first transform circuitry generates a second transformed data word by performing a first invertible operation on the first data word and a second data word. The selection circuitry selects one of the first data word, the first transformed data word, and the second transformed data word based on a first number of bit inversions between the first data word and the second data word, a second number of bit inversions between the first transformed data word and the second data word, and a third number of bit inversions between the second transformed data word and the second data word. The selection circuitry further outputs the selected data word.