公开(公告)号：WO1997009671A1

公开(公告)日：1997-03-13

申请号：PCT/US1996013900

申请日：1996-08-30

Applicant: PHILIPS ELECTRONICS NORTH AMERICA CORPORATION ,  SLAVENBURG, Gerrit ,  VAN DER MUELEN, Pieter ,  CHO, Yong ,  MEHRA, Vijay, K. ,  LEE, Yen, C.

Inventor： PHILIPS ELECTRONICS NORTH AMERICA CORPORATION

IPC: G06F07/38

CPC classification number: G06T1/20 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/3885 ,  G06F15/7832 ,  G06F17/10

Abstract: Custom operations are useable in processor systems for performing functions including multimedia functions. These custom operations enhance a system, such as PC system (TM-1), to provide real-time multimedia capabilities while maintaining advantages of special-purpose, embedded solution, i.e., low cost and chip count, and advantages of a general-purpose processor reprogrammability. These custom operations work in a computer system (TM-1) which supplies input data having operand data, performs operations on the operand data, and supplies result data a destination register (rdes). Operations performed may include audio and video processing including clipping or saturation operations. The present invention also performs parallel operations on select operand data from input registers (rsrc) and stores results in the destination register (rdes).

Abstract translation: 自定义操作在处理器系统中可用于执行包括多媒体功能的功能。 这些定制操作增强了诸如PC系统（TM-1）的系统，以提供实时多媒体功能，同时保持专用，嵌入式解决方案的优点，即低成本和芯片数量以及通用性的优点 处理器可重新编程。 这些定制操作在提供具有操作数数据的输入数据的计算机系统（TM-1）中工作，对操作数数据执行操作，并将结果数据提供给目标寄存器（rdes）。 执行的操作可以包括音频和视频处理，包括剪辑或饱和操作。 本发明还对来自输入寄存器（rsrc）的选择操作数数据执行并行操作，并将结果存储在目标寄存器（rdes）中。

公开(公告)号：WO1995030952A1

公开(公告)日：1995-11-16

申请号：PCT/US1995005436

申请日：1995-05-02

Applicant: ATMEL CORPORATION

Inventor： ATMEL CORPORATION ,  KHONG, James, C., K. ,  MUELLER, Wendey, E. ,  YU, Joe ,  BERGER, Neal ,  GUDGER, Keith, H. ,  GONGWER, Geoffrey, S.

IPC: G06F07/38

CPC classification number: H03K19/1736 ,  H03K19/1737

Abstract: A programmable logic device having a plurality of logic cells (151-15N) arranged in groups defining separate logic regions (111-11N), both regional (191-19N) and multi-regional (13) bus lines, and a crosspoint switch matrix (37) which serves only to route signals from bus lines (391-39J and 401-40L) to inputs of the logic cells (311-31J) without logically combining two or more of the bus signals, i.e. without forming product terms. Rather, all logic is carried out by the logic cells (311-31J) themselves. In particular, the switch matrix (37) is constructed so that each bus line (391-39J and 401-40L) can connect to one or more logic cell inputs, but each logic cell input can meaningfully connect to only one bus line without shorting. In one embodiment, each logic cell (311-31J) feeds one logic signal back (411-41J) to a regional bus line (191) and can potentially feed back another logic signal through its region's universal select matrix (47) to a universal bus line (13). The select matrix (47) connects a subset of the region's potential feedback signals to the universal bus (13).

Abstract translation: 一种可编程逻辑器件，具有多个逻辑单元（151-15N），其以限定单独的逻辑区域（111-11N），区域（191-19N）和多区域（13）总线线路以及交叉点开关矩阵 （37），其仅用于将信号从总线（391-39J和401-40L）传送到逻辑单元（311-31J）的输入，而不逻辑地组合两个或更多个总线信号，即不形成乘积项。 相反，所有逻辑由逻辑单元（311-31J）本身执行。 特别地，开关矩阵（37）被构造成使得每个总线（391-39J和401-40L）可以连接到一个或多个逻辑单元输入，但是每个逻辑单元输入可以有意义地连接到仅一条总线而不短路 。 在一个实施例中，每个逻辑单元（311-31J）将一个逻辑信号（411-41J）馈送到区域总线（191），并且可以将另一个逻辑信号通过其区域的通用选择矩阵（47）反馈到通用 总线（13）。 选择矩阵（47）将该区域的潜在反馈信号的子集连接到通用总线（13）。

公开(公告)号：WO1989006009A1

公开(公告)日：1989-06-29

申请号：PCT/US1988004407

申请日：1988-12-08

Applicant: QUALCOMM, INC.

Inventor： QUALCOMM, INC. ,  KERR, Richard, J. ,  WEAVER, Lindsay, A.

IPC: G06F07/38

CPC classification number: G06J1/00 ,  G06F1/0328 ,  G06F2101/04 ,  G06F2211/902

Abstract: A method and apparatus for reducing spurious output noise in digital frequency synthesizers that employ a sine amplitude converter (16) connected to a Digital-to-Analog converter (18) for generating an analog waveform from sine amplitude data. The method comprises the steps of adding random or pseudorandom numbers which are scaled to have a predetermined magnitude to the sine amplitude data and transferring a resulting addend to the Digital-to-Analog converter (18). The apparatus comprises a summation circuit (22) connected between an output of the sine function converter (18) and an input of the digital-to-analog converter and connected to a random or pseudorandom number generator (24) at a second input. A scale element (26) adjusts the pseudorandom number magnitude to provide numbers having values in the range +/- 1/2 times a minimum quantization step or at least significant bit of the Digital-to-Analog converter (18) resolution where n is greater than or equal to 1.

公开(公告)号：WO1997024657A1

公开(公告)日：1997-07-10

申请号：PCT/US1996016982

申请日：1996-10-23

Applicant: MOTOROLA INC. ,  DWORKIN, James, Douglas ,  BUSS, John, Michael

Inventor： MOTOROLA INC.

IPC: G06F07/38

CPC classification number: G06F7/552 ,  G06F2207/5523

Abstract: A computational array (120) includes at least one computing element (130) that calculates multiple terms in a polynomial. The computing element (130) obtains an input value of each variable in each of the multiple terms and a subscript uniquely identifying the variable. The computing element (130) reads a term identifier and an exponent corresponding to the variable at a memory location based on the subscript. The computing element (130) multiplies the input value by a selected weight value and multiplies the input value by itself a number of times based on the exponent and stores the result at a memory location corresponding to the term identifier. The computing element (130) calculates multiple terms by distinguishing each of the terms with the term identifier.

Abstract translation: 计算阵列（120）包括计算多项式中的多个项的至少一个计算元件（130）。 计算元件（130）获得多个项中的每一个中的每个变量的输入值，以及唯一地标识该变量的下标。 计算元件（130）基于下标在存储器位置读取对应于变量的术语标识符和指数。 计算元件（130）将输入值乘以所选择的权重值，并且基于指数将输入值本身乘以多次，并将结果存储在与术语标识符相对应的存储器位置处。 计算元件（130）通过将每个术语与术语标识符区分开来计算多个术语。

公开(公告)号：WO1995027939A1

公开(公告)日：1995-10-19

申请号：PCT/US1995004354

申请日：1995-04-06

Applicant: MEDIA VISION, INC.

Inventor： MEDIA VISION, INC. ,  COLVIN, Bryan, J., Sr. ,  GOCHNAUER, Daniel, B. ,  COOK, Perry, R.

IPC: G06F07/38

CPC classification number: G10H7/004 ,  G06F15/7857 ,  G10H2250/211

Abstract: A self-contained fully programmable digital signal processor (100) has two processors (101, 102) sharing, in parallel interleave fashion, a math unit (103) such as a multiply-and-accumulate circuit. A background processor (102) controls an external dram and preprocesses the information for a foreground processor (101). On-chip sram (107, 110) stores program parameters for both the foreground and background processors and facilitate information transfer between the foreground and background processors. The sram is time-multiplexed to permit access by the foreground processor, the background processor, and external devices without the expense of multiport sram. Flip-flops maintain data signals to the math unit while the sram is being accessed. The foreground processor has a custom instruction set that optimizes the implementation of complex music synthesis filter structures. An on-chip white noise generator quickly provides pseudorandom data for some of the instructions.

Abstract translation: 独立的完全可编程数字信号处理器（100）具有以并行交错方式共享诸如乘法和累加电路的数学单元（103）的两个处理器（101,102）。 背景处理器（102）控制外部电视并预处理前景处理器（101）的信息。 片上sram（107,110）存储前台和后台处理器的程序参数，并促进前台和后台处理器之间的信息传输。 sram被时分复用以允许前台处理器，后台处理器和外部设备的访问，而不需要多端口sram的费用。 触发器在访问sram时将数据信号保留到数学单元。 前台处理器具有自定义指令集，可以优化复杂音乐合成滤波器结构的实现。 片上白噪声发生器可以快速提供某些指令的伪随机数据。

公开(公告)号：WO1993020502A1

公开(公告)日：1993-10-14

申请号：PCT/US1993002849

申请日：1993-03-22

Applicant: PICKETT, Lester, Caryl

IPC: G06F07/38

CPC classification number: G06F7/483 ,  G06F7/4833

Abstract: An apparatus (255) and method for use in a general purpose computing environment employs particularly efficient exponential and logarithmic function generation in combination with a logarithmic data format to attain general purpose exponential floating-point (E-FLP) numerical processing comparable in effectiveness to conventional floating-point (C-FLP) processing of similar precision and dynamic range. An exponential/logarithmic (E/L) quantity according to the invention has an (E-FLP) value that is inferred from its logarithmic fixed-point (L-FXP) representation value which when employed with exponential and logarithmic data transformation according to the invention yields rapid and precise computational results. E-FLP computations and their associated L-FXP implementations are disclosed, including the elementary transcendental functions. E-FLP computations are characterized by fast multiplication-oriented arithmetic and particularly fast logarithmic and exponential functions, powers and roots.

公开(公告)号：WO1992003778A1

公开(公告)日：1992-03-05

申请号：PCT/US1991005944

申请日：1991-08-20

Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY

Inventor： MASSACHUSETTS INSTITUTE OF TECHNOLOGY ,  PENTLAND, Alex, P.

IPC: G06F07/38

CPC classification number: G06F17/13

Abstract: An apparatus (10) for estimating the solution to a finite element analysis and/or regularization equation, the apparatus including means (12) for generating a pyramid representation of input data, each level of the pyramid representation corresponding to a different set of similar eigenvectors; means (24) for multiplying at least one of the levels of the representation by a weight derived from the eigenvalue associated with the set of eigenvectors for the level to generate a weighted pyramid representation; and means (14) for collapsing the weighted pyramid representation to generate an estimated solution to the equation.

公开(公告)号：WO1991010189A1

公开(公告)日：1991-07-11

申请号：PCT/US1990007351

申请日：1990-12-17

Applicant: MOTOROLA, INC.

Inventor： MOTOROLA, INC. ,  LIU, Clif ,  LINDSLEY, Brett, Louis

IPC: G06F07/38

CPC classification number: G06F7/535 ,  G06F7/4873 ,  G06F7/49957 ,  G06F7/5525 ,  G06F2207/5355

Abstract: A method and a high speed processor (HSP) incorporating that method are set forth for processing signals representing outputs generated by remainderless division algorithms (102) and remainderless square root algorithms so as to obtain rounded outputs (112) conforming to the IEEE 754-1985 binary floating point arithmetic standard. The method and procedure of the present invention allow the solutions of floating-point computations to be rounded such that sign bits, as well as binary bits, of the rounded results are in full compliance with all guidelines of the stated standard.

Abstract translation: 提出了一种结合该方法的方法和高速处理器（HSP），用于处理表示由不剩余分割算法（102）产生的输出的信号和无余数平方根算法，以便获得符合IEEE 754-1985的舍入输出（112） 二进制浮点运算标准。 本发明的方法和过程允许浮点计算的解被舍入，使得舍入结果的符号位以及二进制位完全符合所述标准的所有指导。

公开(公告)号：WO1983001522A1

公开(公告)日：1983-04-28

申请号：PCT/US1982001495

申请日：1982-10-21

Applicant: INTERNATIONAL TELEPHONE AND TELEGRAPH CORPORATION

Inventor： INTERNATIONAL TELEPHONE AND TELEGRAPH CORPORATION ,  KRISHER, Dale, L. ,  CHITSAZ, Sirus

IPC: G06F07/38

CPC classification number: G06F17/10 ,  G06F17/142

Abstract: A digital signal processing apparatus adapted for use with high speed multipliers, which multipliers are known in the prior art. Digital signal processing, in general, is based upon multiplication, summing, subtraction and storing of digital data. Besides multiplication, these functions are performed in the prior art by a large number of integrated circuits resulting in cost, power consumption and reliability problems. The processing register of the present invention performs the remaining arithmetic operations of summing, subtraction, delay and storing of digital data while providing a plurality of different operating modes to accommodate a host different applications. In order to accommodate different modes, the processing register comprises a memory storage register (11) and a computation register (13) which are under the control of a control register (14), which register accepts a control word input having bits thereof indicative of a particular mode of operation.

Abstract translation: 适用于高速乘法器的数字信号处理装置，该乘法器在现有技术中是已知的。 数字信号处理通常基于数字数据的乘法，求和，减法和存储。 除乘法之外，这些功能在现有技术中通过大量集成电路进行，导致成本，功耗和可靠性问题。 本发明的处理寄存器执行数字数据的求和，减法，延迟和存储的剩余算术运算，同时提供多种不同的操作模式以适应主机的不同应用。 为了适应不同的模式，处理寄存器包括在控制寄存器（14）的控制下的存储器存储寄存器（11）和计算寄存器（13），该寄存器接收具有指示其的位的控制字输入 特定的操作模式。

公开(公告)号：WO1982003477A1

公开(公告)日：1982-10-14

申请号：PCT/US1982000392

申请日：1982-03-30

Applicant: MOTOROLA INC

Inventor： MOTOROLA INC ,  BORRAS JAIME ANDRES ,  GONZALEZ RUBEN JESUS ,  SMITH DANIEL MARTIN ,  WIECZOREK ALFRED BRUNO ,  SUAREZ JOSE IGNACIO ,  VICTOR ALAN MICHAEL ,  POPEK MARC HOWARD

IPC: G06F07/38

CPC classification number: H03C3/0966 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0958 ,  H03C3/227 ,  H03D13/005 ,  H03J5/0281 ,  H03K23/66 ,  H03K23/667 ,  H03L7/0802 ,  H03L7/193 ,  H03L7/199 ,  H04B1/405

Abstract: A frequency synthesized transceiver capable of tuning to a plurality of communication channels. The transceiver includes a receiver section (72) and a transmitter section (74) which are coupled to the synthesizer which generates the appropriate injection signals to achieve tuning. The frequency synthesizer includes a multiposition switch (52, 200) which accesses various addressable memory locations in a programmable read-only (60) where the appropriate divisors are stored to cause tuning of the synthesizer to the appropriate communication channel. A zone selector switch (202) enables grouping and easy retrievability of channels. The divisors are supplied to a single synchronous binary swallow counter (46) which works in conjunction with a dual modulus prescaler (44) to monitor the frequency output of the voltage controlled oscillator (42). A programmable divider (32) coupled to a reference oscillator source (30) is compared with the output of the synchronous counter in a digital and analog phase detector (34). The phase detector (34) supplies signals through a loop filter (40) to apply the appropriate voltage to the voltage controlled oscillator (42). The phase detector (34) includes means to rapid advance the voltage controlled oscillator to cause frequency tuning.

Abstract translation: 一种能够调谐到多个通信信道的频率合成收发器。 收发器包括接收器部分（72）和发射器部分（74），其耦合到合成器，其产生适当的注入信号以实现调谐。 频率合成器包括一个多位开关（52,200），该多位开关访问可编程只读（60）中的各种可寻址存储器位置，其中存储适当的除数以使合成器调谐到合适的通信信道。 区域选择器开关（202）使得能够分组并且容易地检索通道。 除数被提供给与双模预分频器（44）一起工作以监视压控振荡器（42）的频率输出的单个同步二进制吞咽计数器（46）。 耦合到参考振荡器源（30）的可编程分频器（32）与数字和模拟相位检测器（34）中的同步计数器的输出进行比较。 相位检测器（34）通过环路滤波器（40）提供信号，以将适当的电压施加到压控振荡器（42）。 相位检测器（34）包括快速前进压控振荡器以引起频率调谐的装置。