PIPELINED REED-SOLOMON DECODER
    1.
    发明申请
    PIPELINED REED-SOLOMON DECODER 审中-公开
    管道式SOLO解码器

    公开(公告)号:WO2007069183A3

    公开(公告)日:2007-09-20

    申请号:PCT/IB2006054745

    申请日:2006-12-11

    CPC classification number: H03M13/1555 H03M13/1515 H03M13/1525 H03M13/6575

    Abstract: Respective symbols of received data words are input (11) in successively-starting symbol cycles. Syndromes for received data words from are computed from the symbols (120), an effect of each received symbol being computed in a respective one of the symbol cycles. The syndromes determine key equations. The key equations are solved and coefficients of an error locator polynomial for the received data word are computed from a combination of syndromes for each received data word in iterative steps (122). Each iterative step is performed in a respective key equation solver cycle. The key equation solver cycles occur at a first average frequency which is lower than a second average frequency of the start of symbol cycles. Corrections to the received data words are computed from solutions of the key equations (124, 126). A correction to each respective symbol being output in a respective one of the symbol cycles. The computing of syndromes, solving and computing corrections is performed pipelined with one another.

    Abstract translation: 接收数据字的相应符号以连续起始的符号周期被输入(11)。 用于从符号(120)计算接收到的数据字的综合征,每个接收到的符号在相应的符号周期中被计算的效果。 综合征确定关键方程。 求解关键方程,并从迭代步骤(122)中针对每个接收到的数据字的校正子的组合计算接收数据字的误差定位多项式的系数。 每个迭代步骤在相应的关键方程求解循环中执行。 关键方程求解器周期发生在低于符号周期开始的第二平均频率的第一平均频率。 根据关键方程(124,126)的解,计算对接收数据字的校正。 每个符号周期中相应的符号周期中输出每个相应符号的校正。 综合症的计算,求解和计算校正是彼此流水线进行的。

    METHODS, SYSTEMS, AND COMPUTER-READABLE MEDIA FOR DECODING CYCLIC CODE
    2.
    发明申请
    METHODS, SYSTEMS, AND COMPUTER-READABLE MEDIA FOR DECODING CYCLIC CODE 审中-公开
    用于解码循环代码的方法,系统和计算机可读介质

    公开(公告)号:WO2017075745A1

    公开(公告)日:2017-05-11

    申请号:PCT/CN2015/093592

    申请日:2015-11-02

    Abstract: A method for decoding a cyclic code is disclosed. The method includes: determining a plurality of syndromes for the cyclic code; determining, by a hardware processor, a first coefficient and a second coefficient based on the plurality of syndromes; determining, by the hardware processor, a third coefficient based on the second coefficient; and generating an error-locator polynomial based on the first coefficient, the second coefficient, and the third coefficient.

    Abstract translation: 公开了一种用于解码循环码的方法。 该方法包括:确定循环码的多个校正子; 由硬件处理器基于所述多个校验子确定第一系数和第二系数; 由所述硬件处理器基于所述第二系数确定第三系数; 并且基于第一系数,第二系数和第三系数生成误差定位器多项式。

    MULTIPLE PASS ERROR CORRECTION PROCESS AND APPARATUS FOR PRODUCT CODES
    3.
    发明申请
    MULTIPLE PASS ERROR CORRECTION PROCESS AND APPARATUS FOR PRODUCT CODES 审中-公开
    多重通过错误校正过程和产品代码的设备

    公开(公告)号:WO1988009966A1

    公开(公告)日:1988-12-15

    申请号:PCT/US1988001698

    申请日:1988-05-27

    Abstract: An error correction system (20) comprises a multi-pass controller (32) which operates through a controller/decoder interface (34) to supervise the execution of decoding passes by a decoder (30). The multi-pass controller (32) employs a correction procedure comprising a plurality of hierarchial strategies S(1), S(2),...S(N) for transitioning the procedure through a plurality of predetermined states. Upon completion of a decoding pass, a pass evaluator (70) evaluates the results of the decoding pass and uses the evaluation for establishing values for further operation. Further passes are executed in accordance with further states determined by the multi-pass controller (32), the further states having particular parameters associated therewith including a strategy selection.

    FLEXIBLE PRBS ARCHITECTURE FOR A TRANSCEIVER
    5.
    发明申请
    FLEXIBLE PRBS ARCHITECTURE FOR A TRANSCEIVER 审中-公开
    灵活的PRBS架构为收发器

    公开(公告)号:WO2014066804A1

    公开(公告)日:2014-05-01

    申请号:PCT/US2013/066885

    申请日:2013-10-25

    CPC classification number: H04L1/0041 G06F7/582 H03M13/1525 H04L25/03866

    Abstract: An apparatus is provided that comprises a polynomial register (510) having a plurality of bits, a first bus, a second bus, and a transceiver (406, 408) that is coupled to the first bus, the second bus, and the polynomial register (510). The polynomial register (510) is configured to store a user-defined polynomial, and the transceiver (406, 408) includes a pseudorandom bit sequence (PRBS) generator (504) that is configured to generate a scrambled signal from the user-defined polynomial and a PRBS checker (508) that is configured to generate a descrambled signal from a second signal using the user-defined polynomial.

    Abstract translation: 提供了一种装置,其包括具有多个位的多项式寄存器(510),第一总线,第二总线和耦合到第一总线,第二总线和多项式寄存器的收发器(406,408) (510)。 多项式寄存器(510)被配置为存储用户定义的多项式,并且收发器(406,408)包括伪随机比特序列(PRBS)生成器(504),其被配置为从用户定义的多项式生成加扰信号 以及PRBS检查器(508),其被配置为使用所述用户定义的多项式从第二信号生成解扰信号。

    PIPELINED ERROR CORRECTING DECODING
    6.
    发明申请
    PIPELINED ERROR CORRECTING DECODING 审中-公开
    管道错误纠正解码

    公开(公告)号:WO2007069183A2

    公开(公告)日:2007-06-21

    申请号:PCT/IB2006/054745

    申请日:2006-12-11

    CPC classification number: H03M13/1555 H03M13/1515 H03M13/1525 H03M13/6575

    Abstract: Respective symbols of received data words are input in successively starting symbol cycles. Syndromes for received data words from are computed from the symbols, an effect of each received symbol being computed in a respective one of the symbol cycles. The syndromes determine key equations. The key equations are solved and coefficients of an error locator polynomial for the received data word are computed from a combination of syndromes for each received data word in iterative steps. Each iterative step is performed in a respective key equation solver cycle. The key equation solver cycles occur at a first average frequency which is lower than a second average frequency of the start of symbol cycles. Corrections to the received data words are computed from solutions of the key equations. A correction to each respective symbol being output in a respective one of the symbol cycles. The computing of syndromes, solving and computing corrections is performed pipelined with one another.

    Abstract translation: 接收的数据字的相应符号以连续的起始符号周期输入。 用于从符号计算的接收到的数据字的综合征,每个接收的符号在相应的符号周期中被计算的效果。 综合征确定关键方程。 求解关键方程,并从迭代步骤中针对每个接收到的数据字的校正子的组合计算接收数据字的误差定位多项式的系数。 每个迭代步骤在相应的关键方程求解循环中执行。 关键方程求解器周期发生在低于符号周期开始的第二平均频率的第一平均频率。 对关键方程的解决方案计算接收数据字的校正。 每个符号周期中相应的符号周期中输出每个相应符号的校正。 综合症的计算,求解和计算校正是彼此流水线进行的。

    DETECTING A SECURITY VIOLATION USING ERROR CORRECTION CODE
    7.
    发明申请
    DETECTING A SECURITY VIOLATION USING ERROR CORRECTION CODE 审中-公开
    使用错误纠正码检测安全违规

    公开(公告)号:WO2006042262A2

    公开(公告)日:2006-04-20

    申请号:PCT/US2005/036630

    申请日:2005-10-11

    CPC classification number: H03M13/1525 G06F11/1044 H03M13/3707

    Abstract: A system and method for detecting a security violation using an error correction code. Some illustrative embodiments may be a method (300) used in a computing system comprising reading a codeword (302) comprising data and an error correction code (ECC) (the ECC associated with the data), deriving an error location polynomial (ELP) from the codeword (304), determining a total number of codeword errors from the ELP (307), and preventing access to the data within the codeword (312) if the total number of codeword errors exceeds a maximum number of correctable errors (308).

    Abstract translation:

    一种使用纠错码检测安全违规的系统和方法。 一些说明性实施例可以是在计算系统中使用的方法(300),该方法包括读取包括数据和纠错码(ECC)(与数据相关联的ECC)的码字(302),从其导出错误位置多项式(ELP) 所述码字(304)确定来自所述ELP(307)的码字错误的总数,并且如果所述码字错误的总数量超过可纠正错误的最大数量(308),则阻止访问所述码字(312)内的所述数据。

    METHODS, SYSTEMS AND COMPUTER-READABLE MEDIA FOR ERROR CORRECTION
    8.
    发明申请
    METHODS, SYSTEMS AND COMPUTER-READABLE MEDIA FOR ERROR CORRECTION 审中-公开
    用于纠错的方法,系统和计算机可读介质

    公开(公告)号:WO2017076301A1

    公开(公告)日:2017-05-11

    申请号:PCT/CN2016/104395

    申请日:2016-11-02

    Abstract: A method for decoding a (n, k, d) cyclic code is disclosed. The method includes: receiving a word corresponding to the cyclic code; constructing a look-up table, wherein the look-up table includes k syndrome vectors and k error patterns; computing a syndrome vector of the received word by a hardware processor; comparing the weight of the syndrome vector of the received word with an error-correcting capacity; decoding the received word by adding the received word and the syndrome vector if the weight of the syndrome vector of the received word is not more than the error-correcting capacity; decoding the received word by inverting bits in the message section in sequence and re-compute a syndrome vector of the inverted received word if the weight of the syndrome vector of the received word is more than the error-correcting capacity.

    Abstract translation: 公开了用于解码(n,k,d)循环码的方法。 该方法包括:接收对应于循环码的单词; 构建查找表,其中查找表包括k个校正子向量和k个错误模式; 由硬件处理器计算所接收的字的校正子向量; 比较接收到的字的征状矢量的权重和纠错能力; 如果所接收的字的校正子向量的权重不大于纠错能力,则通过添加所接收的字和校正子向量来解码所接收的字; 通过顺序反转消息部分中的比特来解码接收的字,并且如果接收到的字的校正子向量的权重大于纠错能力,则重新计算反相的接收字的校正子向量。

    DECODING OF REED - SOLOMON CODES USING LOOK-UP TABLES FOR ERROR DETECTION AND CORRECTION
    9.
    发明申请
    DECODING OF REED - SOLOMON CODES USING LOOK-UP TABLES FOR ERROR DETECTION AND CORRECTION 审中-公开
    REED的解码 - 使用查找表进行错误检测和校正的SOLOMON代码

    公开(公告)号:WO2011154750A1

    公开(公告)日:2011-12-15

    申请号:PCT/GB2011/051092

    申请日:2011-06-13

    Abstract: Systems, methods, and an article of manufacture for decoding a broadcast signal are shown and described. In particular, aspects of the Reed- Solomon decoding algorithm are improved to thereby reduce the amount of processing time required to execute the Reed- Solomon decoding. The improvements concern the use of look-up tables storing pre-computed intermediate results when performing the calculation of syndromes for error detection (250) and when performing the calculation of error locator polynomials and their roots for error correction (260).

    Abstract translation: 示出并描述了用于解码广播信号的系统,方法和制品。 特别地,改进了Reed-Solomon解码算法的方面,从而减少了执行Reed-Solomon解码所需的处理时间量。 这些改进涉及当执行用于错误检测的综合征计算(250)和执行误差定位多项式及其根用于纠错的计算(260)时,使用存储预先计算的中间结果的查找表。

    SYSTEM AND METHOD OF DECODING DATA
    10.
    发明申请
    SYSTEM AND METHOD OF DECODING DATA 审中-公开
    解码数据的系统和方法

    公开(公告)号:WO2011059704A1

    公开(公告)日:2011-05-19

    申请号:PCT/US2010/054224

    申请日:2010-10-27

    Abstract: A decoder is disclosed that can reduce power consumption at different stages of a decoding process. At a first stage where the decoder calculates residual values, the decoder can reduce power consumption by calculating residual values using less than a full set of division circuits. A reduced number of division circuits may be sufficient to successfully calculate residuals associated with the codeword to complete the decoding process. Division circuits that are not used may be disabled to reduce power consumption. At another stage of the decoding process where the decoder generates coefficients that are used to identify locations of errors in the codeword, the decoding process can limit power consumption by reducing the number of iterations of a polynomial generator by incorporating termination decision circuitry.

    Abstract translation: 公开了可以在解码过程的不同阶段降低功耗的解码器。 在解码器计算残差值的第一阶段,解码器可以通过使用少于一整组除法电路计算残差来降低功耗。 减少数量的分割电路可能足以成功地计算与码字相关联的残差以完成解码过程。 未使用的分频电路可能被禁用以降低功耗。 在解码过程的另一阶段,其中解码器产生用于识别码字中的错误位置的系数,解码过程可以通过并入终止判定电路减少多项式生成器的迭代次数来限制功耗。

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