Abstract:
Respective symbols of received data words are input (11) in successively-starting symbol cycles. Syndromes for received data words from are computed from the symbols (120), an effect of each received symbol being computed in a respective one of the symbol cycles. The syndromes determine key equations. The key equations are solved and coefficients of an error locator polynomial for the received data word are computed from a combination of syndromes for each received data word in iterative steps (122). Each iterative step is performed in a respective key equation solver cycle. The key equation solver cycles occur at a first average frequency which is lower than a second average frequency of the start of symbol cycles. Corrections to the received data words are computed from solutions of the key equations (124, 126). A correction to each respective symbol being output in a respective one of the symbol cycles. The computing of syndromes, solving and computing corrections is performed pipelined with one another.
Abstract:
A method for decoding a cyclic code is disclosed. The method includes: determining a plurality of syndromes for the cyclic code; determining, by a hardware processor, a first coefficient and a second coefficient based on the plurality of syndromes; determining, by the hardware processor, a third coefficient based on the second coefficient; and generating an error-locator polynomial based on the first coefficient, the second coefficient, and the third coefficient.
Abstract:
An error correction system (20) comprises a multi-pass controller (32) which operates through a controller/decoder interface (34) to supervise the execution of decoding passes by a decoder (30). The multi-pass controller (32) employs a correction procedure comprising a plurality of hierarchial strategies S(1), S(2),...S(N) for transitioning the procedure through a plurality of predetermined states. Upon completion of a decoding pass, a pass evaluator (70) evaluates the results of the decoding pass and uses the evaluation for establishing values for further operation. Further passes are executed in accordance with further states determined by the multi-pass controller (32), the further states having particular parameters associated therewith including a strategy selection.
Abstract:
An apparatus is provided that comprises a polynomial register (510) having a plurality of bits, a first bus, a second bus, and a transceiver (406, 408) that is coupled to the first bus, the second bus, and the polynomial register (510). The polynomial register (510) is configured to store a user-defined polynomial, and the transceiver (406, 408) includes a pseudorandom bit sequence (PRBS) generator (504) that is configured to generate a scrambled signal from the user-defined polynomial and a PRBS checker (508) that is configured to generate a descrambled signal from a second signal using the user-defined polynomial.
Abstract:
Respective symbols of received data words are input in successively starting symbol cycles. Syndromes for received data words from are computed from the symbols, an effect of each received symbol being computed in a respective one of the symbol cycles. The syndromes determine key equations. The key equations are solved and coefficients of an error locator polynomial for the received data word are computed from a combination of syndromes for each received data word in iterative steps. Each iterative step is performed in a respective key equation solver cycle. The key equation solver cycles occur at a first average frequency which is lower than a second average frequency of the start of symbol cycles. Corrections to the received data words are computed from solutions of the key equations. A correction to each respective symbol being output in a respective one of the symbol cycles. The computing of syndromes, solving and computing corrections is performed pipelined with one another.
Abstract:
A system and method for detecting a security violation using an error correction code. Some illustrative embodiments may be a method (300) used in a computing system comprising reading a codeword (302) comprising data and an error correction code (ECC) (the ECC associated with the data), deriving an error location polynomial (ELP) from the codeword (304), determining a total number of codeword errors from the ELP (307), and preventing access to the data within the codeword (312) if the total number of codeword errors exceeds a maximum number of correctable errors (308).
Abstract:
A method for decoding a (n, k, d) cyclic code is disclosed. The method includes: receiving a word corresponding to the cyclic code; constructing a look-up table, wherein the look-up table includes k syndrome vectors and k error patterns; computing a syndrome vector of the received word by a hardware processor; comparing the weight of the syndrome vector of the received word with an error-correcting capacity; decoding the received word by adding the received word and the syndrome vector if the weight of the syndrome vector of the received word is not more than the error-correcting capacity; decoding the received word by inverting bits in the message section in sequence and re-compute a syndrome vector of the inverted received word if the weight of the syndrome vector of the received word is more than the error-correcting capacity.
Abstract:
Systems, methods, and an article of manufacture for decoding a broadcast signal are shown and described. In particular, aspects of the Reed- Solomon decoding algorithm are improved to thereby reduce the amount of processing time required to execute the Reed- Solomon decoding. The improvements concern the use of look-up tables storing pre-computed intermediate results when performing the calculation of syndromes for error detection (250) and when performing the calculation of error locator polynomials and their roots for error correction (260).
Abstract:
A decoder is disclosed that can reduce power consumption at different stages of a decoding process. At a first stage where the decoder calculates residual values, the decoder can reduce power consumption by calculating residual values using less than a full set of division circuits. A reduced number of division circuits may be sufficient to successfully calculate residuals associated with the codeword to complete the decoding process. Division circuits that are not used may be disabled to reduce power consumption. At another stage of the decoding process where the decoder generates coefficients that are used to identify locations of errors in the codeword, the decoding process can limit power consumption by reducing the number of iterations of a polynomial generator by incorporating termination decision circuitry.