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公开(公告)号：WO2015134819A1
公开(公告)日：2015-09-11
申请号：PCT/US2015/019074
申请日：2015-03-05
Applicant: ORACLE INTERNATIONAL CORPORATION
Inventor： BROOKS, Jeffrey, S. , OLSON, Christopher, H. , MOGHADAM, Hesam, Fathi , EBERGEN, Josephus, C.
CPC classification number: G06F7/483 , G06F5/00 , G06F7/491 , G06F2207/3816 , G06F2207/483 , G06F2207/4912
Abstract: Embodiments of a processor are disclosed for performing arithmetic operations on a machine independent number format. The processor may include a floating point unit, and a number unit. The number format may include a sign/exponent block, a length block, and multiple mantissa digits. The number unit may be configured to perform an operation on two operands by converting the digit format of each mantissa digit of each operand, to perform the operation using the converted mantissa digits, and then to convert each mantissa digit of the result of the operation back into the original digit format.
Abstract translation: 公开了一种用于对机器独立数字格式执行算术运算的处理器的实施例。 处理器可以包括浮点单元和数字单元。 数字格式可以包括符号/指数块，长度块和多个尾数。 数字单元可以被配置为通过转换每个操作数的每个尾数数字的数字格式来执行对两个操作数的操作，以使用转换的尾数来执行操作，然后将操作结果的每个尾数数字转换回 成为原始数字格式。
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2.发明申请
公开(公告)号：WO2021262407A1
公开(公告)日：2021-12-30
申请号：PCT/US2021/035503
申请日：2021-06-02
Applicant: MICRON TECHNOLOGY, INC.
Inventor： YUDANOV, Dmitri , EILERT, Sean, S. , CASTRO, Hernan, A. , MELTON, William, A.
IPC: G11C7/18 , G11C7/12 , G11C8/14 , G11C8/08 , G11C7/06 , G06F7/491 , G06N3/063 , G06F3/0604 , G06F3/0661 , G06F3/0673 , G06N3/04 , G11C11/54 , H03M1/46
Abstract: Methods, apparatuses, and systems for in-or near-memory processing are described. Bits of a first number may be stored on a number of memory elements, wherein each memory element of the number of memory elements intersects a bit line and a word line of a number of word lines. A number of signals corresponding to bits of a second number may be driven on the number of word lines to generate a number of output signals. A value equal to a product of the first number and the second number may be generated based on the number of output signals.
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公开(公告)号：WO2014183195A1
公开(公告)日：2014-11-20
申请号：PCT/CA2014/000420
申请日：2014-05-09
Applicant: UNIVERSITY OF SASKATCHEWAN
Inventor： KO, Seokbum , HAN, Liu
CPC classification number: G06F7/483 , G06F7/4915 , G06F7/5443 , G06F2207/4911
Abstract: A decimal floating-point fused multiplier-adder (DFMA) for carrying out addition and multiplication operations on a first operand, a second operand and a third operand includes a multiplication module for multiplying a first significand of the first operand and a second significand of the second operand to output an intermediate product. The DFMA further includes a pre-alignment module for shifting a third significand of the third operand to output a pre-aligned addend, an addition module for adding the intermediate product and the pre-aligned addend to output an intermediate sum, and a post-alignment module for shifting the intermediate sum based on the shifting of the third significand of the third operand and a preferred exponent to output a post-aligned sum. The post-alignment module of the DFMA may also include a leading non-zero digit detection that receives the intermediate sum as its operand. The post-alignment module of the DFMA may also include a combined rounder-conversion module.
Abstract translation: 一种用于对第一操作数，第二操作数和第三操作数执行加法和乘法运算的十进制浮点融合乘法器加法器（DFMA）包括乘法模块，用于将第一操作数的第一有效位与第一操作数的第二有效数相乘， 第二个操作数输出中间产品。 DFMA还包括预对准模块，用于移动第三操作数的第三有效位数以输出预对准加数，用于将中间乘积和预校准加数相加以输出中间和的加法模块， 对准模块，用于基于第三操作数的第三有效位移和优选指数的移位来移位中间和，以输出后对准和。 DFMA的后对准模块还可以包括接收中间和作为其操作数的前导非零数字检测。 DFMA的后对准模块还可以包括组合的舍入转换模块。
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公开(公告)号：WO2023068489A1
公开(公告)日：2023-04-27
申请号：PCT/KR2022/009974
申请日：2022-07-08
Applicant: 삼성전자 주식회사
Abstract: 일 실시예에 따른 연산 회로는, 복수의 정수들 중 제1 정수 및 제2 정수를 결합하는 결합기를 포함할 수 있다. 상기 연산 회로는, 제1 데이터 타입에 의해 구별되는 부동 소수점 수의 가수들에 대응하는 비트들의 곱을 획득하기 위한 곱셈기를 포함할 수 있다. 상기 복수의 정수들 중 제3 정수가 상기 곱셈기의 제1 포트로 입력될 수 있고, 상기 제1 정수 및 상기 제2 정수의 결합을 나타내는 제4 정수가 상기 곱셈기의 제2 포트로 입력될 수 있다. 상기 연산 회로는, 상기 제1 정수 및 상기 제3 정수의 곱을 나타내는 제6 정수, 및 상기 제2 정수 및 상기 제3 정수의 곱을 나타내는 제7 정수를 출력하는 변환기를 포함하는 연산 회로를 포함할 수 있다.
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公开(公告)号：WO2015200903A1
公开(公告)日：2015-12-30
申请号：PCT/US2015/038189
申请日：2015-06-27
Applicant: ORACLE INTERNATIONAL CORPORATION
Inventor： OLSON, Christopher, H. , BROOKS, Jeffrey, S. , DANYSH, Albert
CPC classification number: G06F9/3001 , G06F7/4917 , G06F9/30014 , G06F9/30025 , G06F9/30029 , G06F9/3802 , G06F2207/4912 , G06F2207/5354
Abstract: Embodiments of an apparatus are disclosed for performing arithmetic operations on provided operands. The apparatus may include a fetch unit, and an arithmetic logic unit (ALU). The fetch unit may be configured to retrieve two operands responsive to receiving an instruction, wherein the operands include binary-coded decimal values. The ALU may be configured to scale a value of each of the operands, and then compress the scaled values of the operands. The compressed values of the operands may include fewer data bits than the corresponding scaled values. The ALU may be further configured to estimate a portion of a result of the operation dependent upon the compressed values of the operands.
Abstract translation: 公开了用于对所提供的操作数执行算术运算的装置的实施例。 该装置可以包括提取单元和算术逻辑单元（ALU）。 提取单元可以被配置为响应于接收到指令而检索两个操作数，其中操作数包括二进制编码的十进制值。 可以将ALU配置为缩放每个操作数的值，然后压缩操作数的缩放值。 操作数的压缩值可以包括比对应的缩放值更少的数据位。 ALU还可以被配置为根据操作数的压缩值来估计操作结果的一部分。
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Patent Agency Ranking
公开(公告)号：WO2011147483A1
公开(公告)日：2011-12-01
申请号：PCT/EP2010/067054
申请日：2010-11-08
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION , SCHWARZ, Eric, Mark , YEH, Phil , COWLISHAW, Michael, Frederic , MUELLER, Silvia, Melitta
CPC classification number: G06F7/49905 , G06F9/30014 , G06F9/30094 , G06F9/3865 , G06F2207/4911
Abstract: A system and method for detecting decimal floating point data processing exceptions. A processor accepts at least one decimal floating point operand and performs a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result. A determination is made as to whether the decimal floating point result fails to maintain a preferred quantum. The preferred quantum indicates a value represented by a least significant digit of a significand of the decimal floating point result. An output is provided, in response to the determining that the decimal floating point result fails to maintain the preferred quantum, indicating an occurrence of a quantum exception. A maskable exception can be generated that is immediately trapped or later detected to control conditional processing.
Abstract translation: 用于检测十进制浮点数据处理异常的系统和方法。 一个处理器接受至少一个十进制浮点运算符，并在至少一个十进制浮点运算符上执行十进制浮点运算，以产生一个十进制浮点运算结果。 确定十进制浮点结果是否不能保持优选的量子。 优选的量子表示由十进制浮点结果的有效位的最低有效位表示的值。 提供输出，响应于确定十进制浮点结果不能保持优选量子，指示量子异常的发生。 可以生成立即捕获或稍后检测到的可屏蔽异常以控制条件处理。
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公开(公告)号：WO2022271608A1
公开(公告)日：2022-12-29
申请号：PCT/US2022/034202
申请日：2022-06-21
Applicant: CEREMORPHIC, INC
Inventor： FINCH, Dylan
Abstract: A floating point multiplier-accumulator (MAC) multiplies and accumulates N pairs of floating point values using N MAC processors operating simultaneously, each pair of values comprising an input value and a coefficient value to be multiplied and accumulated. The pairs of floating point values are simultaneously processed by the plurality of MAC processors, each of which outputs a signed integer form fraction and a maximum exponent. A range estimator forms a possible range of values from the exponent differences and determines an adder precision. The integer form fractions are summed using the adder precision, a sign bit is extracted, and a floating point value is output. Each MAC processor provides its integer form fraction with a precision determined by the MAC processor's exponent difference.
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公开(公告)号：WO2022247194A1
公开(公告)日：2022-12-01
申请号：PCT/CN2021/134297
申请日：2021-11-30
Applicant: 上海阵量智能科技有限公司
Abstract: 本公开提供了一种乘法器、数据处理方法、芯片、计算机设备及存储介质，其中乘法器，包括：控制电路、以及乘法运算电路；其中，所述控制电路，用于确定输入的至少两个第一待处理数据；响应于所述至少两个第一待处理数据中不存在预设数据，将所述至少两个第一待处理数据传输给所述乘法运算电路，并接收所述乘法运算电路传输的结果数据；输出所述结果数据；所述乘法运算电路，用于接收到所述控制电路传输的所述至少两个第一待处理数据时，对所述至少两个第一待处理数据进行乘法处理，得到所述结果数据，并将所述结果数据向所述控制电路传输。
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公开(公告)号：WO2018060041A1
公开(公告)日：2018-04-05
申请号：PCT/EP2017/073877
申请日：2017-09-21
Inventor： MUELLER, Silvia, Melitta, , COPELAND, Reid , BRADBURY, Jonathan , CARLOUGH, Steven
IPC: G06F7/491
Abstract: An instruction to perform a multiply and shift operation is executed. The executing includes multiplying a first value and a second value obtained by the instruction to obtain a product. The product is shifted in a specified direction by a user-defined selected amount to provide a result, and the result is placed in a selected location. The result is to be used in processing within the computing environment.
Abstract translation:
执行执行乘法和移位操作的指令。 执行包括将指令获得的第一值和第二值相乘以获得产品。 产品按指定方向移动一个用户定义的选定量以提供结果，并将结果放置在选定的位置。 结果将用于计算环境中的处理。
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公开(公告)号：WO2018060040A1
公开(公告)日：2018-04-05
申请号：PCT/EP2017/073875
申请日：2017-09-21
Inventor： BRADBURY, Jonathan , COPELAND, Reid , MUELLER, Silvia, Melitta , SCHWARZ, Eric , CARLOUGH, Steven
IPC: G06F7/491
Abstract: An instruction to perform a shift and divide operation is executed. The executing includes shifting a value in a specified direction by a selected amount to provide a dividend, the selected amount being user-defined. The dividend is divided by a divisor to obtain a quotient. At least a subset of the quotient is selected as a result. The result is to be used in processing within the computing environment.
Abstract translation:
执行移位和除法操作的指令。 执行包括将指定方向上的值移动选定的数量以提供股息，所选数量由用户定义。 股息除以除数得到商。 至少选择一个商的子集作为结果。 结果将用于计算环境中的处理。
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