公开(公告)号：WO2023090502A1

公开(公告)日：2023-05-25

申请号：PCT/KR2021/017368

申请日：2021-11-24

Applicant: 서울대학교산학협력단

Inventor： 최완 ,  손경락

IPC: G06F17/16 ,  G06F7/523

Abstract: 본 발명은 프레임 양자화에 기반한 분산 행렬 곱 연산 방법 및 장치에 관한 것으로, 프레임 양자화에 기반한 부호화 컴퓨팅을 이용하여 복수의 연산 노드에서 분산 행렬 곱 연산을 수행하는 방법 및 장치를 제공한다. 이로써 고차원 행렬 곱 처리 성능이 개선된다.

公开(公告)号：WO2022271244A1

公开(公告)日：2022-12-29

申请号：PCT/US2022/022008

申请日：2022-03-25

Applicant: INTEL CORPORATION

Inventor： LANGHAMMER, Martin

IPC: G06F7/523 ,  G06F8/41 ,  G06F7/50 ,  G06F7/5443

Abstract: The present disclosure describes a digital signal processing (DSP) block (26) that includes a columns (102) of weight registers (104) that can receive values and inputs that can receive multiple first values and multiple second values, where the multiple first values may be stored in the weight registers (104) after being received at the inputs. Additionally, the DSP block (26) includes multipliers (108) that, in a first mode of operation, simultaneously multiply each of the first values by a value of the multiple second values. The DSP block (26), in a second mode of operation, enables a first column (102) of multipliers (108) of the multipliers (108) to multiply each of multiple third values by each of multiple fourth values, where at least one of the multiple third values or fourth values includes more bits than the first values and second values.

公开(公告)号：WO2021011316A1

公开(公告)日：2021-01-21

申请号：PCT/US2020/041454

申请日：2020-07-09

Applicant: FACEBOOK TECHNOLOGIES, LLC

Inventor： VENKATESH, Ganesh ,  LAI, Liangzhen ,  CHUANG, Pierce, I-Jen ,  LI, Meng ,  CHANDRA, Vikas

IPC: G06F7/544 ,  G06F7/523

Abstract: Disclosed herein includes a system, a method, and a device including shift circuitry and add circuitry for performing multiplication of a first value and a second value for a neural network. The first value has a predetermined format including a first bit, and two or more second bits to represent a value of zero or 2 n where n is an integer greater than or equal to 0. The device shifts, when the two or more second bits represent the value of 2 n , the second value by (n+1) bits via the shift circuitry to provide a first result, selectively outputs zero or the second value, based on a value of the first bit of the first value, to provide a second result, and adds the first result and the second results via the add circuitry to provide a result of the multiplication of the first and second values.

公开(公告)号：WO2020124694A1

公开(公告)日：2020-06-25

申请号：PCT/CN2019/070318

申请日：2019-01-04

Applicant: 上海大学

Inventor： 金翊 ,  欧阳山 ,  潘志浩 ,  王颖 ,  沈云付 ,  彭俊杰 ,  周时强 ,  刘跃军 ,  陈迅雷

IPC: G06F7/523

Abstract: 一种位数众多、可分组、可重构的多值电子运算器及方法，电子运算器每一位（1、2）有n个列运算器（3、4）和一个电位迭合器（11），每个列运算器（3、4）结构为：A数据输入线接A信号选择器（7）的输入端，A信号选择器（7）的输出端接工作允许器（8）；工作允许器（8）的另一个输入端接重构锁存器（9），工作允许器（8）的输出端还接输出有效器（5）；输出有效器（5）的另一个输入端接电源Vcc，输出有效器（5）输出端接输出生成器（6）；输出生成器（6）的另一个输入端接重构电路（10），输出生成器（6）输出端接电位迭合器（11）；重构电路（10）的两个输入端分别接重构锁存器（9）和B数据输入线；重构锁存器（9）的输入端接重构命令线G；电位迭合器（11）输出端为该运算器位（1、2）的结果信号。写入重构锁存器（9）中的值决定该运算器位（1、2）的逻辑运算规则和是否工作。

公开(公告)号：WO2020081964A1

公开(公告)日：2020-04-23

申请号：PCT/US2019/056985

申请日：2019-10-18

Applicant: FACEBOOK, INC.

Inventor： JOHNSON, Jeffrey, Hoyle

IPC: G06F7/483 ,  G06F7/509 ,  G06F7/523

Abstract: In one embodiment, a method includes receiving a request for an operation to be performed; determining that the operation is associated with a machine-learning algorithm, and in response, route the operation to a computing circuit; performing, at the computing circuit, the operation, including: determining a linear domain product of a first log-domain number and a second log-domain number associated with the operation based on a summation of the first log-domain number and the second log-domain number and output a third log-domain number approximating the linear domain product of the first log-domain number and the second log-domain number; converting the third log-domain number to a first linear-domain number; summing the first linear-domain number and a second linear-domain number associated with the operation, and output a third linear-domain number as the summed result.

公开(公告)号：WO2018071866A1

公开(公告)日：2018-04-19

申请号：PCT/US2017/056668

申请日：2017-10-13

Applicant: FATHOM COMPUTING

Inventor： ANDREGG, William ,  ANDREGG, Michael ,  WEVERKA, Robert, T ,  CLERMONT, Lionel

IPC: G06E1/04 ,  G06F7/523 ,  G06N3/067

CPC classification number: G06E1/045 ,  G02F3/02 ,  G06E3/008 ,  G06G7/16

Abstract: A method and an apparatus optically perform matrix-matrix multiplications in real time utilizing spatially coherent input light and wavelength multiplexing. The method comprises: applying first-matrix values to amplitude of separated and spread light; applying second-matrix values to a combined and spread modulated light; filtering out light that is not part of added amplitudes of light; and separating the added amplitudes of light.

Abstract translation: 一种方法和设备利用空间相干输入光和波长多路复用实时地光学地执行矩阵 - 矩阵乘法。 该方法包括：将第一矩阵值应用于分离和扩展的光的幅度; 将第二矩阵值应用于组合和扩展调制光; 滤出不是所加光幅的一部分的光; 并分离所添加的光的振幅。

公开(公告)号：WO2005096135A3

公开(公告)日：2006-04-06

申请号：PCT/FR2005000443

申请日：2005-02-24

Applicant: FRANCE TELECOM ,  GIRAULT MARC ,  LEFRANC DAVID

Inventor： GIRAULT MARC ,  LEFRANC DAVID

IPC: G06F7/52 ,  G06F7/523 ,  G06F7/58 ,  H04L9/06 ,  H04L9/28 ,  H04L9/32

CPC classification number: H04L9/0662 ,  G06F7/523 ,  H04L9/3247 ,  H04L2209/56

Abstract: The inventive method for performing a cryptographic operation by a device controlled by the security application executed outside thereof consists in producing a cryptographic value (y) in the device by a calculation comprising at least one multiplication between first and second factors containing a security key (s) associated with the device and a challenge number (c) provided by the security application. The first multiplication factor comprises a determined number of bits (L) in a binary representation. The second factor is constrained in such a way that it comprises; in a binary representation, several bits at 1 with a sequence of at least L-1 bits at 0 between each pair of consecutive bits to 1 and the multiplication is carried out by assembling the binary versions of the first factor shifted according to positions of the bits at 1 of the second factor, respectively.

公开(公告)号：WO2005096135A8

公开(公告)日：2005-12-08

申请号：PCT/FR2005000443

申请日：2005-02-24

Applicant: FRANCE TELECOM ,  GIRAULT MARC ,  LEFRANC DAVID

Inventor： GIRAULT MARC ,  LEFRANC DAVID

IPC: G06F7/52 ,  G06F7/523 ,  G06F7/58 ,  H04L9/06 ,  H04L9/28 ,  H04L9/32

CPC classification number: H04L9/0662 ,  G06F7/523 ,  H04L9/3247 ,  H04L2209/56

Abstract: The inventive method for performing a cryptographic operation by a device controlled by the security application executed outside thereof consists in producing a cryptographic value (y) in the device by a calculation comprising at least one multiplication between first and second factors containing a security key (s) associated with the device and a challenge number (c) provided by the security application. The first multiplication factor comprises a determined number of bits (L) in a binary representation. The second factor is constrained in such a way that it comprises; in a binary representation, several bits at 1 with a sequence of at least L-1 bits at 0 between each pair of consecutive bits to 1 and the multiplication is carried out by assembling the binary versions of the first factor shifted according to positions of the bits at 1 of the second factor, respectively.

Abstract translation: 用于由在其外部执行的安全应用程序控制的设备执行密码操作的本发明的方法包括通过包括在第一和第二因素之间的至少一个乘法的计算在设备中产生密码值（y），该密码值包含安全密钥 ）与设备相关联，并且由安全应用程序提供质询号码（c）。 第一乘法因子包括二进制表示中确定的位数（L）。 第二个因素受到限制，它包括： 在二进制表示中，在1处具有几个比特，并且在每对连续比特之间至少有L-1个比特的序列为0，并且乘法是通过组合根据所述比特的位置移位的第一因子的二进制版本 位分别在第二个因子的1处。

公开(公告)号：WO02077792A3

公开(公告)日：2003-03-06

申请号：PCT/GB0201343

申请日：2002-03-21

Applicant: AUTOMATIC PARALLEL DESIGNS LTD ,  TALWAR SUNIL ,  RUMYNIN DMITRIY

Inventor： TALWAR SUNIL ,  RUMYNIN DMITRIY

IPC: G06F7/53 ,  G06F7/52 ,  G06F7/523 ,  G06F17/50

CPC classification number: G06F7/5318

Abstract: A multiplication logic circuit comprises array generation logic and array reduction logic. The array reduction logic comprises array reduction logic for a first level of array reduction which comprises maximal length parallel counters for reducing maximal length columns. The output of the maximal length parallel counters are then further reduced by a second level of reduction logic comprising logic circuits with asymmetric delays in order to compensate for the differential delays experienced by the outputs of the maximal length parallel counters.

Abstract translation: 乘法逻辑电路包括阵列生成逻辑和阵列减少逻辑。 阵列减少逻辑包括用于第一级阵列减少的阵列减少逻辑，其包括用于减小最大长度列的最大长度并行计数器。 然后，最大长度并行计数器的输出通过包括具有非对称延迟的逻辑电路的第二级还原逻辑进一步减小，以便补偿最大长度并行计数器的输出所经历的差分延迟。

公开(公告)号：WO99033276A1

公开(公告)日：1999-07-01

申请号：PCT/DE1998/003118

申请日：1998-10-22

IPC: G06F7/53 ,  G06F1/035 ,  G06F7/52 ,  G06F7/523 ,  G06T9/00 ,  H04N19/126 ,  H04N19/61 ,  H04N7/50

CPC classification number: G06F1/035 ,  G06F7/523 ,  H04N19/124 ,  H04N19/126 ,  H04N19/61

Abstract: The inventive device is used for saving chip area and increasing the processing speed of especially relatively costly multiplication devices which have a displacement device connected downstream, such as those found in video compression devices. To this end, the multiplier is split into a factor part and a displacement part and the displacement part is also taken into account in the displacement unit connected downstream.

Abstract translation: 由装置的手段，特别是在与随后的移位装置相对复杂的乘法器，诸如，例如，发生在视频压缩装置，从而节省了芯片面积和处理速度增加，所述乘数被分成了因子部分和滑动部分和滑动部分在下游移位单元被考虑。