公开(公告)号：WO2016131719A1

公开(公告)日：2016-08-25

申请号：PCT/EP2016/053015

申请日：2016-02-12

Applicant: PHILIPS LIGHTING HOLDING B.V.

Inventor： LIU, Junhu ,  OP HET VELD, Johannes, Hubertus, Gerardus ,  WANG, Binghong ,  HATTRUP, Christian

IPC: G06G7/161 ,  G06G7/163 ,  H05B33/08

CPC classification number: H05B33/0815 ,  G06G7/161 ,  G06G7/163 ,  H05B33/0851 ,  Y02B20/346

Abstract: A level control circuit uses a reference voltage generated from a mains voltage signal by a reference circuit to provide a feedforward control signal. This control signal is used to generate a control signal for controlling a switched mode power converter. The reference circuit comprises a combining circuit adapted to apply a pulse width modulation control signal indicative of said level such that said reference voltage contains the level information. In an embodiment, the reference circuit comprises a voltage divider comprising a resistor circuit and the combining circuit comprises an adjustment module to which a pulse width modulation control signal is applied thereby to change the effective voltage divider ratio to implement level control. The level control further comprises a buffering capacitor or a buffered low pass filter coupled to the output (SET) of the voltage divider. This provides a power factor correction approach for active level control, and which can be implemented very simply and with low cost. It can be used for controlling lighting dimming.

Abstract translation: 电平控制电路使用由参考电路从电源电压信号产生的参考电压来提供前馈控制信号。 该控制信号用于产生用于控制开关模式功率转换器的控制信号。 参考电路包括组合电路，其适于施加指示所述电平的脉宽调制控制信号，使得所述参考电压包含电平信息。 在一个实施例中，参考电路包括一个分压器，该分压器包括一个电阻电路，该组合电路包括一个调整模块，脉宽调制控制信号被施加到该调整模块，从而改变有效分压比以实现电平控制。 电平控制还包括耦合到分压器的输出（SET）的缓冲电容器或缓冲低通滤波器。 这提供了用于主动电平控制的功率因数校正方法，其可以非常简单且成本低廉地实现。 可用于控制照明调光。

公开(公告)号：WO2021055488A1

公开(公告)日：2021-03-25

申请号：PCT/US2020/051087

申请日：2020-09-16

Applicant: ANAFLASH INC.

Inventor： SONG, Seung-Hwan ,  LEE, Sang-Soo ,  KIM, Sihwan

IPC: G06G7/163 ,  G06G7/12 ,  G06G7/16

Abstract: An analog multiplier accumulator array comprises analog multipliers organized in a matrix of rows and columns, each of the multiplier comprising one or more than one analog input signal line coupled to the analog multipliers in a row of the array; an analog level sensing circuit; a set of bit lines, each bit line electrically connected to the analog multiplier in each column of the row; and an analog accumulator configured to connect the set of the bit lines to an analog level sensing circuit for generating digital output signals, wherein an access transistor connected to the analog input line and a variable resistor form the analog multiplier.

公开(公告)号：WO2021225716A1

公开(公告)日：2021-11-11

申请号：PCT/US2021/024558

申请日：2021-03-29

Applicant: QUALCOMM INCORPORATED

Inventor： LU, Ye ,  WANG, Zhongze ,  CHIDAMBARAM, Periannan

IPC: G11C11/54 ,  G11C5/02 ,  G11C7/10 ,  G11C11/412 ,  G11C11/417 ,  G06G7/163 ,  G06N3/063

Abstract: A bit cell circuit of a most-significant bit (MSB) of a multi-bit product generated in an array of bit cells in a compute-in-memory (CIM) array circuit is configured to receive a higher supply voltage than a supply voltage provided to a bit cell circuit of another bit cell corresponding to another bit of the multi-bit product. A bit cell circuit receiving a higher supply voltage increases a voltage difference between increments of an accumulated voltage, which can increase accuracy of an analog-to-digital converter determining a pop-count. A bit cell circuit of the MSB in the CIM array circuit receives the higher supply voltage to increase accuracy of the MSB which increases accuracy of the CIM array circuit output. A capacitance of a capacitor in the bit cell circuit of the MSB is smaller to avoid an increase in energy consumption due to the higher voltage.

公开(公告)号：WO2003012985A3

公开(公告)日：2003-02-13

申请号：PCT/US2002/024093

申请日：2002-07-29

Applicant: SANTEL NETWORKS, INC.

Inventor： CAPOFREDDI, Peter

IPC: G06G7/163

Abstract: An analog multiplier multiplying one analog signal factor with one coefficient factor by decomposing the coefficient factor into a sign signal and a magnitude signal is disclosed.

公开(公告)号：WO2022228883A1

公开(公告)日：2022-11-03

申请号：PCT/EP2022/059708

申请日：2022-04-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED

Inventor： NOWICKI, Tomasz ,  ONEN, Oguzhan, Murat ,  GOKMEN, Tayfun ,  KALANTZIS, Vasileios ,  WU, Chai, Wah ,  SQUILLANTE, Mark ,  RASCH, Malte, Johannes ,  HAENSCH, Wilfried ,  HORESH, Lior

IPC: G06G7/163

Abstract: Techniques are provided to implement hardware accelerated computing of eigenpairs of a matrix. For example, a system includes a processor, and a resistive processing unit coupled to the processor. The resistive processing unit includes an array of cells which include respective resistive devices, wherein at least a portion of the resistive devices are tunable to encode values of a given matrix which is storable in the array of cells. When the given matrix is stored in the array of cells, the processor is configured to determine an eigenvector of the stored matrix by executing a process which includes performing analog matrix-vector multiplication operations on the stored matrix to converge an initial vector to an estimate of the eigenvector of the stored matrix.

公开(公告)号：WO2019169388A1

公开(公告)日：2019-09-06

申请号：PCT/US2019/020549

申请日：2019-03-04

Applicant: SCHIE, David ,  GAITUKEVICH, Sergey ,  DRABOS, Peter ,  SIBRAI, Andreas ,  SIBRAI, Erik

Inventor： SCHIE, David ,  GAITUKEVICH, Sergey ,  DRABOS, Peter ,  SIBRAI, Andreas ,  SIBRAI, Erik

IPC: G06G7/163 ,  G06N3/063

Abstract: A multiplier has a MOSFET in a common source configuration. A MOSFET current source is coupled to a drain terminal of the MOSFET. An inverter has an input coupled to the drain terminal of the MOSFET. An output of the inverter gates two currents whose current magnitudes are proportional. A first capacitor has a first terminal coupled to a first of the two currents and a gate of the MOSFET and a second terminal grounded. A second capacitor has a first terminal coupled to a second of the two currents and a second terminal coupled to the first of the two currents. The multiplier is first reset by discharging a gate capacitance of the MOSFET. In a next reset phase, the second capacitor holds a multiplied value of charge.

公开(公告)号：WO2005013178A1

公开(公告)日：2005-02-10

申请号：PCT/EP2004/008447

申请日：2004-07-28

Applicant: FACHHOCHSCHULE KARLSRUHE ,  SAPOTTA, Hans

Inventor： SAPOTTA, Hans

IPC: G06G7/163

CPC classification number: G06G7/16

Abstract: Die Erfindung betrifft eine Vorrichtung zum analogen Multiplizieren zweier Eingangssignale, umfassend: zumindest einen ersten und zumindest einen zweiten Feldeffekttransistor wobei die beiden Feldeffekttransistoren den gleichen Leitfähigkeitstyp (n-bzw. p-Kanal FET) und einen im wesentlichen gleichen Transkonduktanzfaktor und eine im wesentlichen gleiche Schwellspannung aufweisen und jeweils einen Source-, einen Gate- und einen Drainanschluss aufweisen, wobei der Sourceanschluss des ersten Feldeffekttransistors elektrisch mit dem Sourceanschluss des zweiten Feldeffekttransistors verbunden ist, wobei der Gateanschluss des ersten Feldeffekttransistors einen ersten Eingangsknoten und der Gateanschluss des zweiten Feldeffekttransistors einen zweiten Eingangsknoten bildet und ein erstes V in1 der Eingangssignale als Potentialdifferenz zwischen dem ersten und dem zweiten Eingangsknoten anlegbar ist und ein zweites V in2 der Eingangssignale als Drain-Source-Spannung des ersten Feldeffekttransistors und des zweiten Feldeffekttransistors anlegbar ist; und zumindest eine Stromdifferenzbildungseinrichtung, welche zum Bilden eines dem Produkt der beiden Eingangssignale V in1 , V in2 proportionalem Ausgangssignal Δ I D = I D 1 - I D2 durch Bilden der Differenz zwischen einer Drain-Source-Stromstärke I D1 des ersten Feldeffekttransistors und einer Drain-Source-Stromstärke I D2 des zweiten Feldeffekttransistors ausgelegt ist. Ferner betrifft die Erfindung ein Verfahren zum analogen Multiplizieren zweier Eingangssignale.

Abstract translation: 本发明涉及一种用于模拟乘法的两个输入信号的装置，包括：至少一个第一和至少一个第二场效应晶体管，其中所述两个场效应晶体管相同的导电型的（n型或p沟道FET。）和基本上相同的跨导和一个大致相等的阈值电压 展览和每一个都具有源极，栅极和漏极端子，所述第一场效应晶体管的源极端子电连接到所述第二场效应晶体管的源极端子，所述第一场效应晶体管的栅极形成第一输入节点的第二输入节点和所述第二场效应晶体管的栅极端子 和输入信号的第一VIN1可以用作作为第一Feldeffekttransi的漏极 - 源极电压的第一和第二输入节点和第二Vin2的输入信号之间的电势差 STORS和所述第二场效应晶体管可应用于; 和至少一个电流差值形成装置，其用于形成一个正比于两个输入的乘积信号VIN1，VIN2输出DeltaID = ID1 - ID2通过形成漏极 - 源极的第一场效应晶体管的电流ID1和漏极 - 源极的第二场效应晶体管的电流ID2之间的差 设计。 本发明还涉及一种用于乘以两个模拟输入信号的方法。

公开(公告)号：WO03009078A3

公开(公告)日：2003-04-03

申请号：PCT/DE0202525

申请日：2002-07-10

Applicant: INFINEON TECHNOLOGIES AG ,  TRAENKLE GUENTHER

Inventor： TRAENKLE GUENTHER

IPC: G06G7/163

CPC classification number: G06G7/163

Abstract: The invention relates to a multiplier circuit comprising a multiplier core that contains two cross-coupled transistor pairs (2, 3; 4, 5). According to the invention, a first and a second signal source (10, 11, 13, 14), which are controlled by a first or second signal that is to be multiplied, are respectively connected to control inputs of the transistors (2 to 5) of the multiplier core for inverting the current between the transistor pairs (2, 3; 4, 5), or in a differentiating manner between the transistors (2, 4; 3, 5) of the differential amplifiers. The high degree of symmetry that can be achieved for the input gates of the circuit permits a particularly precise multiplication with excellent linearity. The inventive multiplier can be used, for example, as a high-frequency mixer circuit or as a 90 DEG phase-detector circuit.

Abstract translation: 它是具有两个交叉耦合的晶体管对乘法器芯乘法器（2,3; 4,5），其特征在于，一个第一和一个第二信号源（10，11，13，14），它们由一第一或第二信号驱动到相乘 中，每个连接到控制乘法器的晶体管（2〜5）的输入，用于所述晶体管对之间反转（2,3; 4,5），或在晶体管之间的差分方式（2,4; 3,5）差分放大器的。 由于电路的入口门的可实现高对称性具有良好的线性特别精确的乘法是可能的。 所描述的乘法器被用于例如作为高频混频器电路，或作为90°-Phasendetektorschaltung。

公开(公告)号：WO03005582A3

公开(公告)日：2003-03-13

申请号：PCT/DE0202427

申请日：2002-07-03

Applicant: INFINEON TECHNOLOGIES AG ,  SIMON MARTIN

Inventor： SIMON MARTIN

IPC: G06G7/163

CPC classification number: G06G7/163

Abstract: The invention relates to a multiplier circuit for multiplying two input signals, in which two transistor pairs (2, 3; 4, 5) couple a first input (1, 2) to an output (9, 10) of the multiplier, whereby charge connections of the transistor pairs (2, 3; 4, 5) are connected to a second input (15, 16) of the multiplier via a current mirror (11, 12). The differential amplifier, which is usually provided in Gilbert multipliers is thus omitted, in order to obtain improved noise characteristics of a transmitter assembly comprising a vector modulator, in which the multipliers can preferably be used.

Abstract translation: 它是提供一种用于乘以两个输入信号，乘法器，其中两对晶体管（2,3; 4,5）具有第一输入端（1,2）具有输出（9,10）对中的乘法器，其中所述晶体管对的负载端子（2 ，3; 4，经由电流镜（11，12）到乘法器的第二输入端（15，16）5）相连接。 这消除了在Gilbert乘法器差分放大器的常规设置，使得具有矢量调制器的发射器装置，其中，所述乘法器是优选适用的改进的噪声特性，可制得。