公开(公告)号：WO2021141734A1

公开(公告)日：2021-07-15

申请号：PCT/US2020/065023

申请日：2020-12-15

Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC

Inventor： GARDNER, Geoffrey C. ,  GRONIN, Sergei V. ,  KALLAHER, Raymond L. ,  MANFRA, Michael James

IPC: C30B25/04 ,  C30B25/18 ,  C30B29/40 ,  C30B29/42 ,  C30B29/60 ,  H01L39/00 ,  C30B25/183 ,  H01L21/02381 ,  H01L21/02387 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/02398 ,  H01L21/02455 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/32058 ,  H01L29/0673 ,  H01L29/20 ,  H01L39/22 ,  H01L39/24

Abstract: A nanowire structure includes a substrate, a graded planar buffer layer, a patterned mask, and a nanowire. The graded planar buffer layer is on the substrate. The patterned mask is on the graded planar buffer layer and includes an opening through which the graded planar buffer layer is exposed. The nanowire is on the graded planar buffer layer in the opening of the patterned mask. A lattice constant of the graded planar buffer layer is between a lattice constant of the substrate and a lattice constant of the nanowire. By providing the graded planar buffer layer, lattice mismatch between the nanowire and the substrate can be reduced or eliminated, thereby improving the quality and performance of the nanowire structure.

公开(公告)号：WO2021255426A1

公开(公告)日：2021-12-23

申请号：PCT/GB2021/051485

申请日：2021-06-15

Applicant: UNIVERSITY OF LANCASTER

Inventor： CARRINGTON, Peter ,  DELLI, Evangelia

IPC: H01L21/20 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549

Abstract: A semiconductor device comprises a substrate, one or more first III- semiconductor layers, and a plurality of superlattice structures between the substrate and the one or more first layers. The plurality of superlattice structures comprises an initial superlattice structure and one or more further superlattice structures between the initial superlattice structure and the one or more first layers. The plurality of superlattice structures is configured such that a strain-thickness product of semiconductor layer pairs in each superlattice structure of the one or more further superlattice structures is greater than or equal to a strain-thickness product of semiconductor layer pairs in superlattice structure(s) of the plurality of superlattice structures between that superlattice structure and the substrate. The plurality of superlattice structures is also configured such that a strain-thickness product of semiconductor layer pairs in at least one of the one or more further superlattice structures is greater than a strain-thickness product of semiconductor layer pairs in the initial superlattice structure.