公开(公告)号：WO2023070638A1

公开(公告)日：2023-05-04

申请号：PCT/CN2021/127794

申请日：2021-10-31

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： YANG, Tao ,  ZHAO, Dongxue ,  YANG, Yuancheng ,  XIA, Zhiliang ,  HUO, Zongliang

IPC: H01L29/06 ,  H01L29/786 ,  H01L27/108 ,  H01L21/8242

Abstract: In certain aspects, a memory device includes a vertical transistor, a storage unit, a bit line, and a body line. The vertical transistor includes a semiconductor body extending in a first direction. The semiconductor body includes a doped source, a doped drain, and a channel portion. The storage unit is coupled to a first terminal. The first terminal is one of the source and the drain. The bit line extends in a second direction perpendicular to the first direction and coupled to a second terminal. The second terminal is another one of the source and the drain. The body line is coupled to the channel portion of the semiconductor body.

公开(公告)号：WO2023272620A1

公开(公告)日：2023-01-05

申请号：PCT/CN2021/103730

申请日：2021-06-30

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： CHEN, Liang ,  LIU, Wei ,  WANG, Yanhong ,  XIA, Zhiliang ,  ZHOU, Wenxi ,  ZHANG, Kun ,  YANG, Yuancheng

IPC: H01L25/18

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the second semiconductor structure and the third semiconductor structure. The first semiconductor structure includes an array of NAND memory strings and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a first peripheral circuit of the array of NAND memory strings including a first transistor, and a second semiconductor layer in contact with the first transistor. A third semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a third semiconductor layer in contact with the second transistor. The first peripheral circuit is between the first bonding interface and the second semiconductor layer. The second peripheral circuit is between the second bonding interface and the third semiconductor layer.

公开(公告)号：WO2023272552A1

公开(公告)日：2023-01-05

申请号：PCT/CN2021/103408

申请日：2021-06-30

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： WANG, Yanhong ,  LIU, Wei ,  CHEN, Liang ,  XIA, Zhiliang ,  ZHOU, Wenxi ,  ZHANG, Kun ,  YANG, Yuancheng

IPC: H01L27/1157

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and the second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonding interface and the second semiconductor layer. The polysilicon layer is between the first semiconductor layer and the second semiconductor layer.

公开(公告)号：WO2022198368A1

公开(公告)日：2022-09-29

申请号：PCT/CN2021/082026

申请日：2021-03-22

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： ZHANG, Kun ,  ZHOU, Wenxi ,  XIA, Zhiliang

IPC: H01L27/1157

Abstract: Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a stack structure including interleaved conductive layers and dielectric layers, a doped semiconductor layer, and a channel structure extending through the stack structure and in contact with the doped semiconductor layer. The channel structure includes a composite dielectric film and a semiconductor channel along a first direction. The composite dielectric film includes a gate dielectric portion and a memory portion along a second direction perpendicular to the first direction. A part of the gate dielectric portion faces, along the first direction, one of the conductive layers that is closest to the doped semiconductor layer.

公开(公告)号：WO2021237880A1

公开(公告)日：2021-12-02

申请号：PCT/CN2020/100521

申请日：2020-07-07

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： ZHANG, Kun ,  HUA, Zi Qun ,  ZHOU, Wenxi ,  XIA, Zhiliang ,  HUO, Zongliang

IPC: H01L27/115

Abstract: A 3D memory device (100) includes a substrate (101), a peripheral circuit (108) on the substrate(101), a memory stack (114) including interleaved conductive layers (116) and dielectric layers (118) above the peripheral circuit (108), an N-type doped semiconductor layer (120) above the memory stack (114), a plurality of channel structures (124) each extending vertically through the memory stack (114) into the N-type doped semiconductor layer (120), a conductive layer (122) in contact with upper ends of the plurality of channel structures (124), at least part of which is on the N-type doped semiconductor layer (120), and a source contact (132) above the memory stack (114) and in contact with the N-type doped semiconductor layer (120).

公开(公告)号：WO2021217358A1

公开(公告)日：2021-11-04

申请号：PCT/CN2020/087295

申请日：2020-04-27

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： WU, Linchun ,  LI, Shan ,  XIA, Zhiliang ,  ZHANG, Kun ,  ZHOU, Wenxi ,  HUO, Zongliang

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L21/823487 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/41741

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a P-type doped region of a substrate, an N-type doped semiconductor layer on the P-type doped region, a memory stack including interleaved conductive layers and dielectric layers on the N-type doped semiconductor layer, a channel structure extending vertically through the memory stack and the N-type doped semiconductor layer into the P-type doped region, an N-type doped semiconductor plug extending vertically into the P-type doped region, and a source contact structure extending vertically through the memory stack to be in contact with the N-type doped semiconductor plug.

公开(公告)号：WO2021208195A1

公开(公告)日：2021-10-21

申请号：PCT/CN2020/092513

申请日：2020-05-27

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： WU, Linchun ,  ZHANG, Kun ,  ZHOU, Wenxi ,  XIA, Zhiliang

IPC: H01L27/1157 ,  H01L27/11582

Abstract: 3D memory devices and forming methods thereof are disclosed. A stop layer (203,205), a first polysilicon layer (207), a sacrificial layer (209,211,213), a second polysilicon layer (215), and a dielectric stack (208) are sequentially formed at a first side of a substrate (202). A channel structure (214) extending vertically through the dielectric stack (208), the second polysilicon layer (215), the sacrificial layer (209,211,213), and the first polysilicon layer (207), stopping at the stop layer (203,205), is formed. An opening (224) extending vertically through the dielectric stack (208) and the second polysilicon layer (215), stopping at the sacrificial layer (209,211,213) to expose part of the sacrificial layer (209,211,213), is formed. The sacrificial layer (209,211,213) is replaced, through the opening (224), with a third polysilicon layer (230) between the first and second polysilicon layers (207,215). The substrate (202) is removed from a second side opposite to the first side of the substrate (202), stopping at the stop layer (203,205).

公开(公告)号：WO2021208194A1

公开(公告)日：2021-10-21

申请号：PCT/CN2020/092512

申请日：2020-05-27

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： WU, Linchun ,  ZHANG, Kun ,  ZHOU, Wenxi ,  XIA, Zhiliang

IPC: H01L27/11556

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a stop layer, a polysilicon layer, a memory stack including interleaved stack conductive layers and stack dielectric layers, and a plurality of channel structures each extending vertically through the memory stack and the polysilicon layer, stopping at the stop layer.

公开(公告)号：WO2021189190A1

公开(公告)日：2021-09-30

申请号：PCT/CN2020/080670

申请日：2020-03-23

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： ZHANG, Zhong ,  SUN, Zhongwang ,  ZHOU, Wenxi ,  XIA, Zhiliang

IPC: H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/11578

Abstract: Embodiments of 3D memory devices having staircase structures and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory array structure and a staircase structure in an intermediate of the memory array structure and laterally dividing the memory array structure into a first memory array structure and a second memory array structure. The staircase structure includes a first staircase zone and a bridge structure connecting the first memory array structure and the second memory array structure. The first staircase zone includes a first pair of staircases facing each other in a first lateral direction and at different depths. Each staircase includes a plurality of stairs. At least one stair in the first pair of staircases is electrically connected to at least one of the first memory array structure and the second memory array structure through the bridge structure.

公开(公告)号：WO2021179273A1

公开(公告)日：2021-09-16

申请号：PCT/CN2020/079087

申请日：2020-03-13

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： SUN, Zhongwang ,  ZHANG, Zhong ,  ZHOU, Wenxi ,  LIU, Lei ,  XIA, Zhiliang

IPC: H01L21/768

Abstract: Embodiments of 3D memory structures and methods for forming the same are disclosed. The fabrication method includes disposing an alternating dielectric stack on a substrate, wherein the alternating dielectric stack having first and second dielectric layers alternatingly stacked on top of each other. Next, a plurality of contact openings can be formed in the alternating dielectric stack such that a dielectric layer pair can be exposed inside at least one of the plurality of contact openings. The method further includes forming a film stack of alternating conductive and dielectric layers by replacing the second dielectric layer with a conductive layer, and forming a contact structure to contact the conductive layer in the film stack of alternating conductive and dielectric layers.