公开(公告)号：WO2022241176A1

公开(公告)日：2022-11-17

申请号：PCT/US2022/029120

申请日：2022-05-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： RAHMAN, Hasibur ,  XU, Yang ,  MOCTEZUMA, Ariel, Dario

IPC: H04L27/06 ,  H04B1/06 ,  H03F2200/451 ,  H03F3/19 ,  H03K2005/00078 ,  H03K5/24 ,  H04B1/16

Abstract: An example apparatus includes: a receiver (100) operable to receive a modulated input signal (101) at a receiver input and output a demodulated signal (103) at a receiver output, the receiver (100) comprising a switch (104) having a first current terminal and a first control terminal, the first current terminal coupled to the receiver output. The example apparatus includes a capacitor (110) having a first terminal and a second terminal, the second terminal coupled to the first control terminal and the first terminal coupled to the receiver input. The example apparatus includes a resistor (112) having a third terminal and a fourth terminal, the fourth terminal coupled to the first control terminal. The example apparatus includes a voltage offset source (114) having an input and an output, the output coupled to the third terminal. The example apparatus includes a current source (108) coupled to the first current terminal.

公开(公告)号：WO2021123724A1

公开(公告)日：2021-06-24

申请号：PCT/GB2020/052926

申请日：2020-11-17

Applicant: ARM LIMITED

Inventor： HERBERHOLZ, Rainer ,  WILLIAMS, Peter Andrew Rees

IPC: G06F30/3312 ,  G06F117/10 ,  G06F119/12 ,  G06F1/10 ,  G06F2117/10 ,  G06F2119/12 ,  H03K19/21 ,  H03K2005/00078 ,  H03K5/00

Abstract: A monitoring system for monitoring delay of critical path timing margins can include a plurality of adaptive monitoring circuits, where each adaptive monitoring circuit is coupled to a corresponding one of a plurality of paths in a circuit. Each adaptive monitoring circuit can include a first delay element designed to cause a mean timing margin of the plurality of N paths in the circuit to be within one minimum mean unit delay; a second delay element coupled to the first delay element and designed to add a mean delay of k* σmax; a set-up capture element capturing an output of the second delay element; and a set-up warning comparison element that outputs a set-up warning signal when the output of the set-up capture element and a shadow capture element or a capture element of the corresponding one of the plurality of paths do not satisfy an expected condition.

公开(公告)号：WO2021145970A1

公开(公告)日：2021-07-22

申请号：PCT/US2020/063394

申请日：2020-12-04

Applicant: QUALCOMM INCORPORATED

Inventor： CHAKKIRALA, Subbarao Surendra ,  GALAL, Sherif

IPC: H03K5/133 ,  G06F1/04 ,  G06F1/08 ,  H03F3/217 ,  H03K19/20 ,  H03K2005/00078 ,  H03K2005/00234 ,  H03K3/037 ,  H03K5/00 ,  H03K5/135

Abstract: In certain aspects, a delay circuit includes a multiplexer, a first delay path coupled between an input of the delay circuit and a first input of the multiplexer, and a second delay path coupled between the input of the delay circuit and a second input of the multiplexer. The first delay path includes a first delay device, and the second delay path includes a first inverter, a second delay device, and a second inverter. In other aspects, a delay circuit includes a latch including a first input, a second input, and an output. The first input of the latch is coupled to an input of the delay circuit. The delay circuit also includes a delay path coupled between the input of the delay circuit and the second input of the latch, wherein the delay path includes a pulse generator and a delay device.