公开(公告)号：WO2021011830A1

公开(公告)日：2021-01-21

申请号：PCT/US2020/042425

申请日：2020-07-16

Applicant: LAWRENCE LIVERMORE NATIONAL SECURITY, LLC

Inventor： DEVORE, Peter Thomas Setsuda ,  GOWDA, Apurva Shantharaj ,  PERLMUTTER, David Simon ,  OLSON, Joshua Linne ,  CHOU, Jason Thomas

IPC: H03L7/16 ,  H03L7/191 ,  G04G7/00

Abstract: Methods, devices and systems for providing accurate measurements of timing errors using optical techniques are described. An example timing measurement device includes an optical hybrid that receives two optical pulse trains and produces two or more phase shifted optical outputs. The timing measurement device further includes two or more optical filters that receive the outputs of the optical hybrid to produce multiple pulse signals with distinctive frequency bands. The device also includes one or more photodetectors and analog-to-digital converters to receive to produce electrical signals in the digital domain corresponding to the optical outputs of the hybrid. A timing error associated with the optical pulse trains can be determined using the electrical signals in digital domain based on a computed phase difference between a first frequency band signal and a second frequency band signal and a computed frequency difference between the first frequency band signal and the second frequency band.

公开(公告)号：WO2009109640A3

公开(公告)日：2009-11-05

申请号：PCT/EP2009052634

申请日：2009-03-05

Applicant: CAMBRIDGE SILICON RADIO ,  LAMANNA PASQUALE ,  SORNIN NICOLAS

Inventor： LAMANNA PASQUALE ,  SORNIN NICOLAS

IPC: H03L7/087 ,  H03L7/089 ,  H03L7/095 ,  H03L7/191 ,  H03L7/197

CPC classification number: H03L7/095 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/191 ,  H03L7/1974

Abstract: A phase-locked loop for generating an output signal that has a predetermined frequency relationship with a reference signal, the phase-locked loop comprising a signal generator arranged to generate the output signal, a charge pump arranged to generate current pulses for controlling the signal generator, two control units for controlling a duration of the current pulses generated by the charge pump and a selection unit arranged to select either the first control unit or the second control unit to control the charge pump, wherein a first one of the control units is arranged to continuously monitor a phase-difference between the reference signal and a feedback signal formed from the output signal and to, when selected by the selection unit, control the charge pump to output a current pulse having a duration that is dependent on that phase-difference and a second one of the control units is arranged to, when selected by the selection unit, control the charge pump to output a current pulse of predetermined duration that compensates for a phase error in the feedback signal.

Abstract translation: 一种用于产生与参考信号具有预定频率关系的输出信号的锁相环，所述锁相环包括布置成产生所述输出信号的信号发生器;电荷泵，被布置成产生用于控制信号发生器的电流脉冲 用于控制由电荷泵产生的电流脉冲的持续时间的两个控制单元和布置成选择第一控制单元或第二控制单元以控制电荷泵的选择单元，其中控制单元中的第一个被布置 以连续地监视参考信号和从输出信号形成的反馈信号之间的相位差，并且当由选择单元选择时，控制电荷泵输出具有取决于该相位差的持续时间的电流脉冲 并且所述控制单元中的第二个被布置成当由所述选择单元选择时，控制所述电荷泵输出电流脉冲 的预定持续时间来补偿反馈信号中的相位误差。

公开(公告)号：WO02009289A2

公开(公告)日：2002-01-31

申请号：PCT/US2001/015144

申请日：2001-05-10

IPC: H03L7/089 ,  H03L7/191 ,  H03L7/00

CPC classification number: H03L7/089 ,  H03L7/191

Abstract: A phase locked loop (PLL) circuit is provided having a DC biasing circuit that enables the PLL to operate with a single power supply voltage, and which also eliminates the dead hone associated with the phase detector of the PLL. The PLL includes a phase detector for detecting the phase difference between a reference clock signal and a feedback signal and for generating phase pulse outputs corresponding to this phase difference, an integrator coupled to the phase pulse outputs for generating a phase voltage in proportion to the pulse width of the phase pulse outputs, and a voltage controlled oscillator coupled to the phase voltage for generating a local oscillator signal that is synchronized to the reference clock signal and which is coupled to the feedback signal. The DC biasing circuit generates a variable pulse width bias signal that is merged with the phase pulse outputs in order to polarize the integrator inputs at a particular DC bias level. In a first embodiment, the DC biasing circuit merges the variable pulse width bias signal with both positive and negative phase outputs from the phase detector in order to polarize the integrator. In a second embodiment, the DC biasing circuit merges the variable pulse width bias signal with only one of the positive or the negative phase outputs from the phase detector in order to simultaneously polarize the integrator and to eliminate the dead zone associated with the phase detector by injecting a continuous phase error into the PLL feedback signal.

Abstract translation: 提供了具有DC偏置电路的锁相环（PLL）电路，其使PLL能够以单个电源电压工作，并且还消除了与PLL的相位检测器相关联的死机。 PLL包括用于检测参考时钟信号和反馈信号之间的相位差并用于产生对应于该相位差的相位脉冲输出的相位检测器，耦合到相位脉冲输出的积分器，用于产生与脉冲成比例的相电压 相位脉冲输出的宽度以及耦合到相位电压的压控振荡器，用于产生与参考时钟信号同步并且与反馈信号相耦合的本地振荡器信号。 DC偏置电路产生与相位脉冲输出合并的可变脉冲宽度偏置信号，以便在特定DC偏置电平下使积分器输入偏振。 在第一实施例中，DC偏置电路将可变脉冲宽度偏置信号与来自相位检测器的正相和负相输出合并，以使积分器偏振。 在第二实施例中，DC偏置电路将可变脉冲偏置信号与来自相位检测器的正相或负相输出中的一个合并，以便同时使积分器极化并消除与相位检测器相关的死区， 将连续相位误差注入到PLL反馈信号中。

公开(公告)号：WO00045515A1

公开(公告)日：2000-08-03

申请号：PCT/JP2000/000390

申请日：2000-01-26

IPC: H03L7/087 ,  H03L7/089 ,  H03L7/095 ,  H03L7/107 ,  H03L7/191 ,  H03L7/08

CPC classification number: H03L7/191 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/107 ,  Y10S331/02

Abstract: A PLL apparatus comprises a variable frequency-division device (111) for frequency-dividing the output of a voltage-controlled oscillator (112), reference signal generating means (105) for generating a first reference signal and a second reference signal of different phase, a first comparator (106) for comparing the phase of the first reference signal with that of the output of the variable frequency-division device (111), a second comparator (110) for comparing the phase of the second reference signal with that of the output of the variable frequency-division device (111), a detector (118) for detecting a locked state, and a control unit (117). With this construction, the phases are compared, when not in a locked state, at different timings by the plural comparators. Therefore the locking time is shortened by performing plural phase comparisons for one period of the reference signal. In a locked state, moreover, the phases are compared by one comparator, so that an increase in power consumption, as might otherwise be caused by multiple stages of loop, can be suppressed.

Abstract translation: PLL装置包括用于对压控振荡器（112）的输出进行分频的可变分频装置（111），用于产生第一参考信号的参考信号产生装置（105）和不同相位的第二参考信号 ，用于比较第一参考信号的相位与可变分频装置（111）的输出的相位的第一比较器（106）;第二比较器（110），用于将第二参考信号的相位与 可变分频装置（111）的输出，用于检测锁定状态的检测器（118）和控制单元（117）。 利用这种结构，当不是处于锁定状态时，通过多个比较器在不同的定时比较相位。 因此，通过对参考信号的一个周期执行多个相位比较来缩短锁定时间。 此外，在锁定状态下，通过一个比较器比较相位，从而可以抑制由多个环路引起的功率消耗的增加。

公开(公告)号：WO2023278083A2

公开(公告)日：2023-01-05

申请号：PCT/US2022/031632

申请日：2022-05-31

Applicant: QUALCOMM INCORPORATED

Inventor： LIM, Younghyun ,  TANG, Yiwu ,  PARK, Dongmin ,  ZHU, Yunliang ,  KESKIN, Mustafa ,  CHAO, Yue

IPC: H03K21/08 ,  H03K23/66 ,  H03L7/24 ,  H03L7/193 ,  H03L7/183 ,  H03K23/667 ,  H03L7/0995 ,  H03L7/191

Abstract: Aspects of the disclosure relate to a ring oscillator (RO) frequency divider configured to frequency divide an input clock by a programmable divider ratio to generate an output clock. In this regard, the RO frequency divider receives the input clock, enables each of a ring of N cascaded inverter stages substantially one at a time in response to the input clock; and outputs a second clock from an output of one of the ring of N cascaded inverter stages. In one aspect, each stage includes a p-channel metal oxide semiconductor field effect transistor (PMOS FET) coupled in series with an n-channel metal oxide semiconductor field effect transistor (NMOS FET). In another, each stage includes two PMOS FETs and an NMOS FET.

公开(公告)号：WO2009109603A1

公开(公告)日：2009-09-11

申请号：PCT/EP2009/052561

申请日：2009-03-04

Applicant: CAMBRIDGE SILICON RADIO LIMITED ,  LAMANNA, Pasquale ,  SORNIN, Nicolas

Inventor： LAMANNA, Pasquale ,  SORNIN, Nicolas

IPC: H03L7/087 ,  H03L7/089 ,  H03L7/191 ,  H03L7/197

CPC classification number: H03L7/087 ,  H03L7/0891 ,  H03L7/191 ,  H03L7/1974

Abstract: A phase-locked loop arranged to generate an output signal having a first frequency that is a static value times the frequency of a reference signal, the phase-locked loop comprising a signal generator arranged to generate the output signal, a divider arranged to receive the output signal and divide the output signal to form a feedback signal, the divider being arranged to vary the divisor by which the output signal is divided to cause the output signal to have a frequency that is said static value times the frequency of the reference signal, a comparison unit arranged to compare the feedback signal with the reference signal, one or more current generators arranged to output current pulses in dependence on said comparison, a summation unit arranged to receive the current pulses output by the current generator(s) and form a single current pulse therefrom and a loop filter arranged to filter the single current pulse to form a control signal for controlling the signal generator, the phase-locked loop being arranged such that the current generator(s) generate(s) a first current pulse dependent on a phase-difference between the feedback signal and the reference signal and a second current pulse whose magnitude and sign are dependent on an error in the feedback signal that is caused by the variation of the divisor, and the summation unit receives the first and second current pulses and stores an electrical charge representative of those current pulses and the summation unit outputs a single current pulse dependent on the electrical charge stored by the summation unit, said single current pulse being representative of a phase-difference that would have existed between the reference signal and the feedback signal if the feedback signal had been formed by dividing the output signal by said static value and not by the varied divisor.

Abstract translation: 一种锁相环，被布置成产生具有作为静态值的第一频率乘以参考信号的频率的输出信号，该锁相环包括布置成产生输出信号的信号发生器， 输出信号并分频输出信号以形成反馈信号，所述分频器被布置成改变所述输出信号被分频的除数，使得输出信号具有所述静态值的频率乘以参考信号的频率， 比较单元，其被布置为将反馈信号与参考信号进行比较，一个或多个电流发生器被布置为根据所述比较输出电流脉冲;一个求和单元，被布置成接收由电流发生器输出的电流脉冲并形成 单电流脉冲和环路滤波器被布置为滤波单电流脉冲以形成用于控制信号发生器的控制信号， 锁定环被布置成使得电流发生器产生取决于反馈信号和参考信号之间的相位差的第一电流脉冲，以及第二电流脉冲，其幅度和符号取决于 由除数的变化引起的反馈信号，并且求和单元接收第一和第二电流脉冲并存储代表那些电流脉冲的电荷，并且求和单元输出单个电流脉冲，这取决于由 如果反馈信号是通过将输出信号除以所述静态值而不是通过变数除数形成的，则所述单电流脉冲表示将存在于参考信号和反馈信号之间的相位差。

公开(公告)号：WO2005099095A1

公开(公告)日：2005-10-20

申请号：PCT/EP2005/004317

申请日：2005-04-06

Applicant: EADS TELECOM ,  ROBBE, Michel

Inventor： ROBBE, Michel

IPC: H03L7/191

CPC classification number: H03L7/191 ,  H03L7/085 ,  H03L7/1974

Abstract: An oscillator supplies a high frequency signal f vco to a frequency divider. A phase comparator produces a signal measuring the phase difference between the divided frequency signal (QA) and a reference signal at a comparison frequency f ref . A low-pass filter controls the oscillator from the measurement signal. To enable a high frequency signal to be synthesized such that f vco = P x f ref, where P is the sum of an integer value (Po) and of a deviation value (ΔP) relative to said integer value which corresponds to a modulo 0.5 number, a digital frequency divider is constructed to generate a measurement window (#n-l, #n, #n+l) on each cycle of the divided frequency signal, the duration of which corresponds alternately to an even number then to an odd number of cycles of the high frequency signal.

Abstract translation: 振荡器将高频信号fvco提供给分频器。 相位比较器产生测量分频信号（QA）与比较频率fref的参考信号之间的相位差的信号。 低通滤波器根据测量信号控制振荡器。 为了使得能够合成高频信号，使得fvco = P×fref，其中P是相对于对应于模数0.5数的所述整数值的整数值（Po）和偏差值（DeltaP）之和， 数字分频器被构造成在分频信号的每个周期上产生测量窗口（#n1，#n，＃n + 1），其持续时间交替地对应于偶数，然后对应于奇数个周期 高频信号。

公开(公告)号：WO02019550A3

公开(公告)日：2002-06-06

申请号：PCT/US2001/027188

申请日：2001-08-31

IPC: H03L7/07 ,  H03L7/087 ,  H03L7/089 ,  H03L7/191 ,  H03L7/23 ,  H04J3/06

CPC classification number: H03L7/0891 ,  H03L7/07 ,  H03L7/087 ,  H03L7/191 ,  H03L7/23 ,  H04J3/0685

Abstract: An improved digital-data receiver synchronization apparatus and method is provided wherein memory devices in the receiver such as phase-lock loops are provided with composite phase-frequency detectors, mutually cross-connected comparison feedback means, or both, to provide robust reception of digital data signals. The apparatus and method are preferably utilized with synchronous architecture wherein a single master clock is used to provide frequency signals to the memory devices, and also can be used with asynchronous architecture. The apparatus and method provide fast lock-up times in moderately to severely noisy conditions and have improved tolerances to clock asymmetries.

Abstract translation: 提供了一种改进的数字数据接收机同步装置和方法，其中诸如锁相环的接收机中的存储器件被提供有复合相位频率检测器，相互交叉连接的比较反馈装置或两者，以提供对数字 数据信号。 该装置和方法优选地利用同步架构，其中使用单个主时钟来向存储器件提供频率信号，并且还可以与异步架构一起使用。 该装置和方法在中等至严重的噪声条件下提供快速的锁定时间，并且具有改善的时钟不对称公差。

公开(公告)号：WO2006112797A1

公开(公告)日：2006-10-26

申请号：PCT/SG2006/000099

申请日：2006-04-18

Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH ,  LIM, Teck, Hwee ,  YIN, Jee, Khoi ,  CHIA, Yan, Wah, Michael

Inventor： LIM, Teck, Hwee ,  YIN, Jee, Khoi ,  CHIA, Yan, Wah, Michael

IPC: H03L7/191 ,  H01Q3/38

CPC classification number: H03L7/18 ,  H01Q3/30 ,  H01Q3/38 ,  H03L7/0805 ,  H03L7/0891

Abstract: A time delay apparatus for generating a plurality of phase shifted signals is described comprising a phase tuner generating a phase control signal and a phase interpolator receiving at least one digital signal and generating the plurality of phase shifted signals by. phase shifting the digital signal according to the phase control signal.

Abstract translation: 描述了一种用于产生多个相移信号的时间延迟装置，包括产生相位控制信号的相位调谐器和接收至少一个数字信号的相位内插器，并通过相位信号产生多个相移信号。 根据相位控制信号对数字信号进行相移。

公开(公告)号：WO02056476A1

公开(公告)日：2002-07-18

申请号：PCT/JP2002/000211

申请日：2002-01-15

IPC: H03L7/08 ,  H03L7/087 ,  H03L7/089 ,  H03L7/095 ,  H03L7/191 ,  H03L7/193 ,  H03L7/197 ,  H03L7/22

CPC classification number: H03L7/087 ,  H03L7/0802 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/191 ,  H03L7/193 ,  H03L7/1974 ,  H03L2207/18

Abstract: A PLL circuit comprises a reference signal generating unit (2) for generating reference signals of different phases, variable frequency dividers (12) for dividing the frequency of the output signal of a voltage-controlled oscillator (VCO) and thereby outputting feedback signals, and a phase comparator (13) for comparing the phase of each feedback signal with that of the corresponding reference signal and thereby outputting phase comparison signals. When the output signal is synchronized with a preset frequency signal, at least one variable frequency divider (4) of the variable frequency dividers (12) is operated, and the operation of the other (8) is stopped.

Abstract translation: PLL电路包括用于产生不同相位的参考信号的参考信号产生单元（2），用于分压压控振荡器（VCO）的输出信号的频率的可变分频器（12），从而输出反馈信号，以及 相位比较器（13），用于将每个反馈信号的相位与对应的参考信号的相位进行比较，从而输出相位比较信号。 当输出信号与预设频率信号同步时，可变分频器（12）的至少一个可变分频器（4）被操作，并且另一个（8）的操作被停止。