公开(公告)号：WO2017151290A1

公开(公告)日：2017-09-08

申请号：PCT/US2017/017264

申请日：2017-02-09

Applicant: QUALCOMM INCORPORATED

Inventor： SAPUTRA, Nitz ,  LEE, Sang Min ,  SEO, Dongwon

IPC: H03B5/26

CPC classification number: H03B5/26 ,  H03B5/04

Abstract: Circuits and methods for compensating variation in an amplitude-regulated oscillator are provided. In one example, the oscillator includes a diode clamp having back-to-back diode-connected transistors with body terminals. Circuits and methods modulate a body-source voltage of the diode-connected transistors to compensate for process, temperature, and voltage variation.

Abstract translation: 提供了用于补偿幅度调节振荡器中的变化的电路和方法。 在一个示例中，振荡器包括具有与体端子连接的背对背二极管连接的晶体管的二极管钳位。 电路和方法调制二极管连接的晶体管的体源电压以补偿过程，温度和电压变化。

公开(公告)号：WO2023049620A1

公开(公告)日：2023-03-30

申请号：PCT/US2022/075860

申请日：2022-09-01

Applicant: QUALCOMM INCORPORATED

Inventor： MAHMOUDIDARYAN, Parisa ,  SAPUTRA, Nitz ,  SEO, Dongwon ,  MEHDIZAD TALEIE, Shahin

IPC: H03M1/06 ,  H03M1/66

Abstract: Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. One example device for digital-to-analog conversion generally includes: a digital-to-analog converter (DAC) having an input coupled to an input node of the device; a first retum-to-zero (RZ) DAC having an input coupled to an input node of the device; and a combiner, wherein an output of the first DAC is coupled to a first input of the combiner, and wherein an output of the first RZ DAC is coupled to a second input of the combiner.

公开(公告)号：WO2010108032A1

公开(公告)日：2010-09-23

申请号：PCT/US2010/027859

申请日：2010-03-18

Applicant: QUALCOMM INCORPORATED ,  SEO, Dongwon ,  WADHWA, Sameer

Inventor： SEO, Dongwon ,  WADHWA, Sameer

IPC: H03L1/00 ,  H03K3/011 ,  H03K3/03

CPC classification number: H03L1/00 ,  H03K3/0322

Abstract: An integrated circuit incorporating a bias circuit for a current-controlled oscillator (ICO) with improved power supply rejection ratio (PSRR) is described. The bias circuit for the ICO includes two error amplifiers. The first error amplifier regulates the bias voltage, VBN, referenced to a ground supply (GND). The second error amplifier regulates the bias voltage, VBP, referenced to a positive power supply (VDD). The VBP and VBN bias voltages have improved PSRR relative to conventional ICO bias circuits for noise injected into VDD and GND.

Abstract translation: 描述了具有改善的电源抑制比（PSRR）的电流控制振荡器（ICO）的偏置电路的集成电路。 ICO的偏置电路包括两个误差放大器。 第一个误差放大器调节参考接地电源（GND）的偏置电压VBN。 第二个误差放大器调节参考正电源（VDD）的偏置电压VBP。 相对于常规ICO偏置电路，VBP和VBN偏置电压对于注入VDD和GND的噪声具有改进的PSRR。

公开(公告)号：WO2008157295A1

公开(公告)日：2008-12-24

申请号：PCT/US2008/066839

申请日：2008-06-13

Applicant: QUALCOMM Incorporated ,  SEO, Dongwon ,  SUN, Bo ,  SAHOTA, Gurkanwal Singh (Kamal) ,  MISHRA, Manu

Inventor： SEO, Dongwon ,  SUN, Bo ,  SAHOTA, Gurkanwal Singh (Kamal) ,  MISHRA, Manu

IPC: H03M1/00

CPC classification number: H03M1/002 ,  H03M1/682 ,  H03M1/747

Abstract: A digital-to-analog converter, RF transmit channel and method, for converting a digital signal of N bits having a set M of most significant bits and a set L of least significant bits to an analog signal, are disclosed. The digital signal defines a set of coded values which are converted to analog values and modulated on to a RF signal. The digital-to-analog converter includes a plurality of switches and an output stage, for providing at least a first differential output signal and a second differential output signal. The output stage modifies currents received from the plurality of switches, such that the value of the average output current of the first and second differential outputs signals is steered to a relatively low current value at the mid-point of the coded values.

Abstract translation: 公开了用于将具有最高有效位的集合M的N位的数字信号和最低有效位的集合L转换为模拟信号的数模转换器，RF发送信道和方法。 数字信号定义了一组编码值，它们被转换为模拟值并被调制到RF信号上。 数模转换器包括多个开关和输出级，用于至少提供第一差分输出信号和第二差分输出信号。 输出级修改从多个开关接收的电流，使得第一和第二差分输出信号的平均输出电流的值被转向在编码值的中点处的相对低的电流值。

公开(公告)号：WO2023278923A1

公开(公告)日：2023-01-05

申请号：PCT/US2022/072698

申请日：2022-06-01

Applicant: QUALCOMM INCORPORATED

Inventor： MEHDIZAD TALEIE, Shahin ,  SEO, Dongwon ,  SWAMINATHAN, Ashok ,  SAHOTA, Gurkanwal Singh ,  WEIL, Andrew ,  FEI, Haibo

IPC: H03M1/74 ,  H03M1/12 ,  H03M1/78 ,  H03M1/002 ,  H03M1/1295 ,  H03M1/466 ,  H03M1/502 ,  H03M1/742 ,  H03M1/747 ,  H03M1/785

Abstract: Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) system. The DAC system generally includes a plurality of current steering cells, each comprising a current source coupled to at least two current steering switches, wherein control inputs of the at least two current steering switches are coupled to an input path of the DAC system. The DAC system may also include a current source toggle circuit configured to selectively disable the current source of at least one of the plurality of current steering cells, and a feedforward path coupled between the input path and at least one control input of the current source toggle circuit.

公开(公告)号：WO2022094521A1

公开(公告)日：2022-05-05

申请号：PCT/US2021/071838

申请日：2021-10-13

Applicant: QUALCOMM INCORPORATED

Inventor： LIU, Xilin ,  MAHMOUDIDARYAN, Parisa ,  MEHDIZAD TALEIE, Shahin ,  RASHIDI, Negar ,  SEO, Dongwon

IPC: H03M1/10 ,  H03K5/05 ,  H03K5/156 ,  H03M1/66 ,  H03K5/00

Abstract: Certain aspects of the present disclosure generally relate to circuitry and techniques for digital -to-analog conversion. For example, certain aspects provide an apparatus for digital-to-analog conversion. The apparatus generally includes a mixing-mode digital-to-analog converter (DAC), a duty cycle adjustment circuit having an input coupled to an input clock node and having an output coupled to a clock input of the mixing-mode DAC, and a current comparison circuit having inputs coupled to outputs of the mixing-mode DAC and having an output coupled to a control input of the duty cycle adjustment circuit.

公开(公告)号：WO2016122836A1

公开(公告)日：2016-08-04

申请号：PCT/US2016/012072

申请日：2016-01-04

Applicant: QUALCOMM INCORPORATED

Inventor： JI, Honghao ,  SEO, Dongwon

IPC: H01L27/02 ,  H01L23/60 ,  H01L23/62 ,  H02H11/00 ,  H02H9/04

CPC classification number: H02H3/18 ,  H01L27/0266 ,  H01L27/0292 ,  H02H11/003

Abstract: A reverse current protection (RCP) circuit is provided that includes an RCP switch coupled between a power supply rail and a buffer power supply node. A control circuit powered by a buffer supply voltage on the buffer power supply node controls the RCP switch to open in response to a discharge of a power supply voltage carried on the power supply rail.

Abstract translation: 提供了一个反向电流保护（RCP）电路，其包括耦合在电源轨和缓冲电源节点之间的RCP开关。 由缓冲器电源节点上的缓冲器电源供电的控制电路控制RCP开关响应于在电源轨上承载的电源电压的放电而打开。

公开(公告)号：WO2015183496A1

公开(公告)日：2015-12-03

申请号：PCT/US2015/029535

申请日：2015-05-06

Applicant: QUALCOMM INCORPORATED

Inventor： LEE, Sang Min ,  SEO, Dongwon

IPC: H03M1/06 ,  H03M1/08 ,  H03M1/68 ,  H03M1/78

CPC classification number: H03M1/0863 ,  H03M1/0612 ,  H03M1/0881 ,  H03M1/687 ,  H03M1/785

Abstract: The apparatus may be an N-bit DAC including (2M-1) parallel stages associated with M most significant bits, and (N-M) stages associated with (N-M) least significant bits. The (2M-1) parallel stages may deliver a first current to current-summing nodes of the DAC. The (N-M) stages may include a resistive network and a second pair of switches, and may deliver a second current to the resistive network of the stage. Each resistive network may scale the respectively delivered currents according to a binary weight of a stage corresponding to the resistive network, and may deliver the scaled currents to the pair of current-summing nodes. At least one of the (N-M) stages may be separated from the remaining stages.

Abstract translation: 该装置可以是包括与M个最高有效位相关联的（2M-1）个并行级和与（N-M）个最低有效位相关联的（N-M）级的N位DAC。 （2M-1）并联级可以将第一电流传送到DAC的电流求和节点。 （N-M）级可以包括电阻网络和第二对开关，并且可以将第二电流传递到级的电阻网络。 每个电阻网络可以根据对应于电阻网络的级的二进制权重来缩放分别传递的电流，并且可以将缩放的电流传送到一对电流求和节点。 （N-M）级中的至少一个可以与其余级分离。

公开(公告)号：WO2020236557A1

公开(公告)日：2020-11-26

申请号：PCT/US2020/033071

申请日：2020-05-15

Applicant: QUALCOMM INCORPORATED

Inventor： MEHDIZAD TALEIE, Shahin ,  SAPUTRA, Nitz ,  JIANG, Chen ,  SEDIGHI, Behnam ,  CHAMAS, Ibrahim Ramez ,  ASURI, Bhushan Shanti ,  SEO, Dongwon

IPC: H04B1/04 ,  H03M1/66

Abstract: A radio frequency digital-to-analog converter (RF-DAC) transmitter is provided that includes an in-phase channel, a quadrature-phase channel, a first intermediate-phase channel, and a second intermediate-phase channel. Each channel is configured to convert a respective baseband signal to an RF signal where each channel includes a pair of interleaved RF-DACs for producing a pair of interleaved RF signals and a subtractor.

公开(公告)号：WO2016137646A1

公开(公告)日：2016-09-01

申请号：PCT/US2016/015193

申请日：2016-01-27

Applicant: QUALCOMM INCORPORATED

Inventor： NADERI ALIZADEH, Mohammadhossein ,  MEHDIZAD TALEIE, Shahin ,  SEO, Dongwon

IPC: H03M3/04

CPC classification number: H03M1/0626 ,  H03M1/002 ,  H03M1/687 ,  H03M3/368 ,  H03M3/502 ,  H03M7/3042

Abstract: In one embodiment, a method for converting an input digital signal into an analog signal is provided. The method comprises modulating the input digital signal into a modulated digital signal, and converting the modulated digital signal into the analog signal using a digital-to-analog converter (DAC). The modulation shapes quantization noise of the DAC to place a notch at a frequency within an out-of-bound frequency band to reduce the quantization noise within the out-of-bound frequency band.

Abstract translation: 在一个实施例中，提供了一种将输入数字信号转换为模拟信号的方法。 该方法包括将输入数字信号调制成调制数字信号，并使用数模转换器（DAC）将调制数字信号转换为模拟信号。 该调制形成DAC的量化噪声，以将陷波置于超限频带内的频率，以减小超出频带内的量化噪声。