公开(公告)号：WO2022212222A2

公开(公告)日：2022-10-06

申请号：PCT/US2022/022076

申请日：2022-03-27

Applicant: CYBERUS LABS SP. Z O.O. ,  WOLOSEWICZ, Jack

Inventor： WOLOSEWICZ, Jack

IPC: G06F21/60 ,  G06F9/32 ,  G06F9/54 ,  G06F21/78 ,  G06F21/602 ,  G06F9/321 ,  G06F9/544

Abstract: Briefly, an encryption/decryption algorithm providing for consistent encryption entropy and encryption/decryption performance that is independent of the type of input data. The methods disclosed utilize two randomized lookup buffers, a key buffer and an offset buffer, as well as a histogram buffer. The two lookup buffers are initialized with a secret key shared (identical seed value) between the Client/Server (Or Hub/Device in the loT world).

公开(公告)号：WO2022050999A1

公开(公告)日：2022-03-10

申请号：PCT/US2021/035060

申请日：2021-05-31

Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC

Inventor： HASKINS, John William, Jr.

IPC: G06F9/32 ,  G06F9/38

Abstract: Exemplary aspects disclosed herein include detecting a repetitive pattern in an instruction pipeline of a processor to reduce repeated fetching. The processor includes a pattern record circuit configured to receive information in a data stream (e.g., instructions or consumed data) in the instruction pipeline. The pattern record circuit includes a first in, first out (FIFO) table circuit that contains an input record column and plurality of additional adjacent record columns. As new data occurs in the data stream, the data record circuit is configured to sequentially record next incoming data from the data stream into a next input entry of an input record column and then shift previously recorded data into adjacent entries of adjacent record columns. The distance between the input record column and the additional record column that has matching data is the distance in the data stream between a reoccurrence of data in the data stream.

公开(公告)号：WO2021181712A1

公开(公告)日：2021-09-16

申请号：PCT/JP2020/015665

申请日：2020-04-07

Applicant: オムロン株式会社

Inventor： 村田　融 ,  八木　大介 ,  上村　敦史 ,  田中　裕 ,  谷口　拓也 ,  小林　雄作

IPC: G06F9/32 ,  G06F11/16 ,  G06F11/18 ,  G06F21/52

Abstract: プロセッサは、退避命令に応じて、レジスタのデータをメモリの第１の領域に退避させ、復帰命令に応じて、第１の領域のデータをレジスタに復帰させる。プロセッサは、退避命令の実行後に、第１の領域のデータを、メモリにおける第２の領域から第Ｎの領域の各々に書き込む。プロセッサは、復帰命令の実行前に、第１の領域から第Ｎの領域のデータを互いに照合し、過半数の領域のデータが一致し、かつ、第１の領域のデータが過半数の領域のデータと一致しないことに応じて、過半数の領域のデータを第１の領域に上書きする。これにより、レジスタからメモリに一時退避されるデータの破損に起因する、システムの一時的な停止を抑制できる。

公开(公告)号：WO2021036173A1

公开(公告)日：2021-03-04

申请号：PCT/CN2020/071560

申请日：2020-01-11

Applicant: 创新先进技术有限公司

Inventor： 刘晓建

IPC: G06F9/38 ,  G06F9/32

Abstract: 本说明书实施例提供一种解释执行字节码指令流的方法和装置，通过虚拟机的解释器实现，其中利用第一寄存器存储下一条指令的模拟函数地址，利用第二寄存器存储当前指令的模拟函数地址。在方法中，首先读取第一寄存器中存储的第一值；当第一值为有效值时，将第一值存储到第二寄存器中，作为字节码指令流中当前指令对应的当前模拟函数地址。然后，从存储器获取当前指令的下一条指令对应的下一模拟函数地址，并将该下一模拟函数地址存储在第一寄存器中，并且，根据从第二寄存器中读取的当前模拟函数地址，执行当前指令。

公开(公告)号：WO2020167388A1

公开(公告)日：2020-08-20

申请号：PCT/US2020/012455

申请日：2020-01-07

Applicant: AXIS SEMICONDUCTOR, INC.

Inventor： WANG, Xiaolin ,  WU, Qian

IPC: G06F9/54 ,  G06F9/32

Abstract: A method of synchronizing thread execution of a host and one or more coprocessors includes writing by the host of an event command and at least one coprocessor instruction to a FIFO and comparing of the event command with a current event register of the coprocessor until they match, whereupon the FIFO entries are popped and the instructions are forwarded to the coprocessor for execution. A plurality of entry groups can be written to the FIFO, each beginning with an event command. The instructions can direct the coprocessor to exchange data with shared memory and apply its thread to the received data. The processors and shared memory can be linked by a ring-type bus having a controller that performs the comparison, popping, and instruction forwarding. The coprocessor clears the current event register during thread execution, and then writes an event command to the register when processing is complete.

公开(公告)号：WO2020041276A1

公开(公告)日：2020-02-27

申请号：PCT/US2019/047217

申请日：2019-08-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： KOCEV, Andrej ,  FLEISCHMAN, Jay ,  TROESTER, Kai ,  CHU, Johnny C. ,  WILKENS, Tim J. ,  MARKETKAR, Neil ,  LONG, Michael W.

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32

Abstract: Systems and methods selectively bypass address-generation hardware in processor instruction pipelines. In an embodiment, a processor includes an address-generation stage and an address-generation-bypass-determination unit (ABDU). The ABDU receives a load/store instruction. If an effective address for the load/store instruction is not known at the ABDU, the ABDU routes the load/store instruction via the address-generation stage of the processor. If, however, the effective address of the load/store instruction is known at the ABDU, the ABDU routes the load/store instruction to bypass the address-generation stage of the processor.

公开(公告)号：WO2019196776A9

公开(公告)日：2019-10-17

申请号：PCT/CN2019/081699

申请日：2019-04-08

Applicant: C-SKY MICROSYSTEMS CO., LTD.

Inventor： JIANG, Tao ,  GUO, Yubo ,  WANG, Manzhou ,  WEI, Dingyan

IPC: G06F9/30 ,  G06F9/32

Abstract: A processor (100) achieving a zero-overhead loop, the processor (100) comprising an instruction stream control circuitry (110) and a loop control circuitry (120), wherein the loop control circuitry (120) comprises a loop address detecting circuitry (122) and a loop end determining circuitry (124). Eliminating, by means of combining instructions and hardware, additional control instructions required by each loop iteration and achieving loop acceleration with zero overhead, thereby improving the loop execution efficiency.

公开(公告)号：WO2019021177A1

公开(公告)日：2019-01-31

申请号：PCT/IB2018/055500

申请日：2018-07-24

Applicant: MMAPRO IT SOLUTIONS (PTY) LTD

Inventor： MSIZA, Ishmael Sbusiso

IPC: G06F9/32 ,  G06F9/34 ,  G06K9/62

Abstract: The invention relates to a method of matching fingerprint images, the method comprising the steps of: providing data relating to a pre-registered, minutiae query template of a first, query fingerprint image; providing data relating to a pre-registered, minutiae reference template of a second, reference fingerprint image; comparing the data relating to the pre-registered, minutiae template and pre-registered, minutiae reference template; and generating data relating to a match score based on the number of fingerprint minutiae of the pre-registered, minutiae query template that matches the fingerprint minutiae of the pre-registered, minutiae reference template of the second, reference fingerprint image.

公开(公告)号：WO2017112401A1

公开(公告)日：2017-06-29

申请号：PCT/US2016/065120

申请日：2016-12-06

Applicant: QUALCOMM INCORPORATED

Inventor： KOTHINTI NARESH, Vignyan Reddy ,  PRIYADARSHI, Shivam ,  DAMODARAN, Raguram

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38

CPC classification number: G06F9/30058 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/325 ,  G06F9/3802 ,  G06F9/3808 ,  G06F9/381 ,  G06F9/3867

Abstract: Selective storing of previously decoded instructions of frequently-called instruction sequences in an instruction sequence buffer to be executed by a processor is disclosed. In one aspect, a selective instruction sequence buffer controller is configured to selectively store previously decoded instructions for an instruction sequence by determining if a received instruction address corresponds to an instruction sequence captured in an instruction sequence buffer. If the received instruction address corresponds to a captured instruction sequence, the selective instruction sequence buffer controller provides corresponding micro-operations stored in the instruction sequence buffer for execution. If the received instruction address does not correspond to the captured instruction sequence, the selective instruction sequence buffer controller reduces a frequency indicator of the instruction sequence. The selective instruction sequence buffer controller may also increase the frequency indicator of the instruction sequence when the instruction sequence is accessed, capturing the instruction sequence once the frequency indicator meets a threshold.

Abstract translation: 公开了将由处理器执行的指令序列缓冲器中的经常调用的指令序列的先前解码的指令的选择性存储。 在一个方面中，选择性指令序列缓冲器控制器被配置为通过确定接收到的指令地址是否对应于在指令序列缓冲器中捕获的指令序列来选择性地存储用于指令序列的先前经解码的指令。 如果所接收的指令地址对应于捕获的指令序列，则选择性指令序列缓冲器控制器提供存储在指令序列缓冲器中的相应的微操作以供执行。 如果接收到的指令地址不对应于捕获到的指令序列，则选择指令序列缓冲器控制器减少指令序列的频率指示符。 当指令序列被访问时，选择指令序列缓冲器控制器也可以增加指令序列的频率指示符，一旦频率指示符满足阈值就捕获指令序列。

公开(公告)号：WO2017064455A1

公开(公告)日：2017-04-20

申请号：PCT/GB2016/052836

申请日：2016-09-14

Applicant: ARM LIMITED

Inventor： STEPHENS, Nigel John

IPC: G06F9/30 ,  G06F9/32

CPC classification number: G06F9/30036 ,  G06F9/30043 ,  G06F9/325

Abstract: A vector data transfer instruction is provided for triggering a data transfer between storage locations corresponding to a contiguous block of addresses and multiple data elements of at least one vector register. The instruction specifies a start address of the contiguous block using a base register and an immediate offset value specifies as a multiple of the size of the contiguous block of addresses. This is useful for loop unrolling which can help to improve performance of vectorised code by combining multiple iterations of a loop into a single iteration of an unrolled loop, to reduce the loop control overhead.

Abstract translation: 提供矢量数据传输指令，用于触发对应于至少一个向量寄存器的连续地址块和多个数据元素的存储位置之间的数据传输。 该指令使用基址寄存器指定连续块的开始地址，并且立即偏移值指定为连续地址块的大小的倍数。 这对循环展开非常有用，它可以通过将多次迭代的循环组合到展开循环的单个迭代中来帮助提高矢量化代码的性能，从而减少循环控制开销。