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    METHODS AND SYSTEMS FOR REDUCING ECC POWER CONSUMPTION
    1.
    发明申请
    METHODS AND SYSTEMS FOR REDUCING ECC POWER CONSUMPTION 审中-公开

    公开(公告)号：WO2022185091A1

    公开(公告)日：2022-09-09

    申请号：PCT/IB2021/020011

    申请日：2021-03-02

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： LAURENT, Christophe Vincent Antoine

    IPC: G11C29/42 ,  G11C29/52 ,  G06F11/10

    Abstract: The present disclosure relates to a method for operating an array of memory cells, the method comprising the steps of storing user data in a plurality of memory cells of the memory array, storing parity data associated with the user data in a number of parity cells of the memory array, the parity data corresponding to one of a plurality of selectable Error Correction Code (ECC) correction capabilities from a minimum ECC correction capability to a maximum ECC correction capability, calculating an ECC syndrome from the stored user data and parity data, based on the ECC syndrome, determining a number of errors in the data, and, based on the determined number of errors, selecting an ECC correction capability of the plurality of ECC correction capabilities. Related memory devices and systems are also herein disclosed.

    APPARATUS WITH LATCH CORRECTION MECHANISM AND METHODS FOR OPERATING THE SAME
    2.
    发明申请
    APPARATUS WITH LATCH CORRECTION MECHANISM AND METHODS FOR OPERATING THE SAME 审中-公开

    公开(公告)号：WO2022108763A1

    公开(公告)日：2022-05-27

    申请号：PCT/US2021/058124

    申请日：2021-11-04

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： HE, Yuan ,  LI, Jiyun

    IPC: G11C29/00 ,  G11C29/52

    Abstract: Methods, apparatuses, and systems related to an apparatus are described. The apparatus may include (1) a fuse array configured to provide non-volatile storage of fuse data and (2) local latches configured to store the fuse data during runtime of the apparatus. The apparatus may further include an error processing circuit configured to determine error detection-correction data for the fuse data. The apparatus may subsequently broadcast data stored in the local latches to the error processing circuit to determine, using the error detection-correction data, whether the locally latched data has been corrupted. The error processing circuit may generate corrected data to replace the locally latched data based on determining corruption in the locally latched data.

    SELECTIVE WORDLINE SCANS BASED ON A DATA STATE METRIC
    3.
    发明申请
    SELECTIVE WORDLINE SCANS BASED ON A DATA STATE METRIC 审中-公开

    公开(公告)号：WO2022103702A1

    公开(公告)日：2022-05-19

    申请号：PCT/US2021/058469

    申请日：2021-11-08

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： RAYAPROLU, Vamsi Pavan ,  MUCHHERLA, Kishore Kumar ,  SINGIDI, Harish R. ,  ALSASUA, Gianni S.

    IPC: G11C16/08 ,  G11C16/10 ,  G11C29/52 ,  G06F11/10

    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including identifying, among a first plurality of wordlines of a set of pages of the memory device, at least one wordline having a current value of a data state metric satisfying a first condition; determining new values of the data state metric of a second plurality of wordlines of the set of pages, wherein the at least one wordline is excluded from the second plurality of wordlines; and responsive to determining that the new values of the data state metric of one or more wordlines of the second plurality of wordlines satisfy a second condition, performing a media management operation with respect to the one or more wordlines.

    存储器测试方法
    4.
    发明申请
    存储器测试方法 审中-公开

    公开(公告)号：WO2022077971A1

    公开(公告)日：2022-04-21

    申请号：PCT/CN2021/105582

    申请日：2021-07-09

    Applicant: 长鑫存储技术有限公司

    Inventor： 许小峰

    IPC: G11C29/52 ,  G11C11/406 ,  G11C11/4078

    Abstract: 一种存储器测试方法，所述方法包括：确定目标存储库的刷新周期T、设计抵御攻击频率F以及单行读取时间t（S1）；根据刷新周期T、设计抵御攻击频率F以及单行读取时间t确定攻击行数N（S2）；根据所述攻击行数N的值在目标存储库中确定一组目标攻击行，所述一组目标攻击行包括N个目标攻击行，所述N个目标攻击行中的至少两个目标攻击行之间间隔一行（S3）；连续X次读取所述N个目标攻击行后，检测所述目标攻击行的全部相邻行是否发生数据异常以完成一次攻击测试（S4）；在M个所述刷新周期内对所述目标存储库完成MT/NXt次所述攻击测试，在所述攻击测试均未发生数据异常时，判断所述目标存储库抵御攻击能力达标（S5）。

    LIFE EXPECTANCY MONITORING FOR MEMORY DEVICES
    6.
    发明申请
    LIFE EXPECTANCY MONITORING FOR MEMORY DEVICES 审中-公开

    公开(公告)号：WO2022026125A1

    公开(公告)日：2022-02-03

    申请号：PCT/US2021/040334

    申请日：2021-07-02

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： VAN DE GRAAFF, Scott, D. ,  PLUM, Todd, Jackson ,  SCHAEFER, Scott, E. ,  BOEHM, Aaron, P. ,  INGRAM, Mark, D.

    IPC: G11C29/50 ,  G11C29/52 ,  G06F11/00

    Abstract: Methods, systems, and devices for life expectancy monitoring for memory devices are described. Some memory devices may degrade over time, and this degradation may include or refer to a reduction of an ability of the memory device to reliably store, read, process, or communicate information, among other degradation. In accordance with examples as disclosed herein, a system may include components configured for monitoring health or life expectancy of the memory device, such as components that perform comparisons between signals or other operating characteristics resulting from operating at the memory device and one or more threshold values that may be indicative of a life expectancy of the memory device. In various examples, a memory device may perform a subsequent operation based on such a comparison, or may provide an indication of a life expectancy to a host device based on one or more comparisons or determinations about health or life expectancy.

    A NEW BITCELL FOR DATA REDUNDANCY
    7.
    发明申请
    A NEW BITCELL FOR DATA REDUNDANCY 审中-公开

    公开(公告)号：WO2022015431A1

    公开(公告)日：2022-01-20

    申请号：PCT/US2021/036367

    申请日：2021-06-08

    Applicant: QUALCOMM INCORPORATED

    Inventor： LEE, Hochul ,  KOTA, Anil Chowdary ,  SRIKANTH, Anne

    IPC: G11C29/00 ,  G11C17/14 ,  G11C17/18 ,  G11C5/00 ,  G11C29/52

    Abstract: The present disclosure provides bit cells with data redundancy according to various aspects. In certain aspects, a bit cell includes a first memory element coupled to a write bit line, and a first write-access switch coupled between the first memory element and a ground. The bit cell also includes a second memory element coupled to the write bit line, and a second write-access switch coupled between the second memory element and the ground. The bit cell further includes a read-access switch coupled between the first memory element and a read bit line, wherein a control input of the read-access switch is coupled to a read-select line.

    一种复位系统、数据处理系统以及相关设备
    9.
    发明申请
    一种复位系统、数据处理系统以及相关设备 审中-公开

    公开(公告)号：WO2021259351A1

    公开(公告)日：2021-12-30

    申请号：PCT/CN2021/102029

    申请日：2021-06-24

    Applicant: 华为技术有限公司

    Inventor： 刁阳彬 ,  韩林

    IPC: G06F12/02 ,  G06F11/10 ,  G11C29/52

    Abstract: 本申请实施例公开了一种复位系统、数据处理系统以及相关设备，该方法可用于管理内存数据的领域中。复位系统包括复位控制电路、处理器内核和第一寄存器，第一寄存器记录的故障替换信息中包括第一存储单元的位置信息，第一存储单元为在对内存中的存储单元进行故障替换时存在故障的存储单元。复位控制电路响应获取到的复位信号，向第二模块发送复位指令，第二模块包括处理器内核且不包括第一模块。提出故障替换信息这一新概念，并增设专门记录故障替换信息的第一寄存器，在完成复位操作之后，能够根据故障替换信息，正确访问内存中的数据，以实现在使用内存中的故障替换技术和复位技术的前提下，内存中数据的不丢失。

    記憶装置
    10.
    发明申请
    記憶装置 审中-公开

    公开(公告)号：WO2021124638A1

    公开(公告)日：2021-06-24

    申请号：PCT/JP2020/036871

    申请日：2020-09-29

    Applicant: ソニーセミコンダクタソリューションズ株式会社

    Inventor： 手塚　宙之 ,  黒田　真実

    IPC: G11C13/00 ,  G11C7/14 ,  G11C29/52 ,  G11C11/16

    Abstract: 記憶装置の状態に応じて、読出しに使用する基準電位を柔軟に設定する。　データメモリセル群は、データを記憶する。参照メモリセル群は、複数の参照電位を記憶する。基準電位生成部は、参照メモリセル群に記憶される複数の参照電位から所定数の参照電位を選択して、基準電位を生成する。参照電位選択制御部は、所定の条件に従って基準電位生成部における選択を制御する。センスアンプは、基準電位を基準としてデータメモリセル群から読み出されたデータを増幅する。

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