US09503266B2
A method includes receiving a first linearity ciphertext that represents a first biometric template encrypted using a relational linearity encryption scheme. The method includes receiving a second linearity ciphertext that represents a second biometric template encrypted using the relational linearity encryption scheme. The method includes discovering a linearity relationship between the first and second linearity ciphertexts using a linearity relational secret key. The method includes receiving a first proximity ciphertext that represents the first biometric template encrypted using a relational proximity encryption scheme. The method includes receiving a second proximity ciphertext that represents the second biometric template encrypted using the relational proximity encryption scheme. The method includes detecting a proximity between the first and second proximity ciphertexts in terms of a Hamming distance using a proximity relational secret key and authenticating an identity of a user based upon the proximity and the linearity relationship.
US09503263B2
A method for distributing data to a plurality of storage locations in a computing network is provided. The method includes receiving, at a processor in the computing network, input data and an input random cryptovariable, transforming, at the processor, the input data and the input random cryptovariable into encrypted output using Da Yen processing, and distributing the encrypted output to the plurality of storage locations. The present design further includes a method for decrypting encrypted blocks of data distributed over a plurality of storage locations in a computing network. The method includes receiving, at a processor in the computing network, a plurality of cipher/key word pairs, and transforming, at the processor, the plurality of cipher/key word pairs and a salt key word into plaintext using Da Yen processing.
US09503260B2
According to an aspect of the invention, a security token for facilitating access to a remote computing service via a mobile device is conceived, said security token comprising an NFC interface, a smart card integrated circuit and a smart card applet stored in and executable by said smart card integrated circuit, wherein the smart card applet is arranged to support a cryptographic challenge-response protocol executable by the mobile device.
US09503252B2
Some embodiments relate to a phase interpolator. The phase interpolator includes a control block to provide a plurality of phase interpolation control signals which are collectively indicative of a phase difference between a first clock and a second clock. The phase interpolation control signals define different phase step sizes by which the first clock is to be phase shifted to limit the phase difference. A plurality of Gilbert cells provide a plurality of current levels, respectively, based on the plurality of phase interpolation control signals. A plurality of current control elements adjust the plurality of current levels from the plurality of Gilbert cells. The plurality of current levels are adjusted by different amounts for the different phase step sizes.
US09503251B2
Methods and apparatus for mitigating baseline wander in an AC coupled transmission line are provided. An apparatus includes an input node, an output node, a sampling circuit and a level-shifting output circuit. The input and output nodes couple the apparatus in parallel with a high-pass filter of the transmission line. The sampling circuit samples an input voltage at the input node. The level-shifting output circuit delivers a level-shifted version of the input voltage to the output node. The apparatus may include a first pair of synchronized switches, a second pair of synchronized switches, and a sampling capacitor therebetween. The switches are driven periodically with concurrent closure of the two pairs of switches inhibited. The sampling capacitor couples between a signal input and a reference node upon closure of the first pair of switches, and between a bias voltage and a signal output upon closure of the second pair of switches.
US09503247B2
A computer device may include logic configured to configure carrier aggregation for a user equipment serviced by the base station device; activate a secondary component carrier for the user equipment; determine that a quality level for the secondary component carrier is lower than a quality threshold; and de-activate the secondary component carrier for the user equipment, in response determining that the quality level is lower than the quality threshold. The logic may be further configured to detect a problem associated with the primary component carrier for the user equipment; determine whether a better primary component carrier is available, in response to detecting the problem; switch to the better primary component carrier, when the better primary component carrier is available; and de-configure carrier aggregation for the user equipment, when the better primary component carrier for the user equipment is not available.
US09503237B2
A radio network node (28) comprises a transmitter/receiver (48, 82, 93) configured to communicate over an air interface (32) with a wireless terminal (30); a scheduler (46, 84); and a order signal determination means (46, 62, 84). The scheduler (46, 84) schedules pilot signals, including common pilot signals transmitted for channel estimation, for transmission over the air interface to the wireless terminal. The order signal determination means (46, 62, 84) is configured to make a selective determination whether additional pilot signals for data demodulation are also to be transmitted to the wireless terminal (30) in addition to the common pilot signals transmitted for the channel estimation. The wireless terminal (30) comprises a transmitter and receiver (50, 101, 112) and pilot selection means (68). The pilot selection means (68) is configured to make a determination regarding which pilot signals transmitted by the radio network node are to be utilized by the wireless terminal. The pilot signals transmitted by the radio network node include common pilot signals transmitted for channel estimation and additional pilot signals transmitted for data demodulation.
US09503235B2
A method of transmitting channel state information (CSI)-reference signals (RS) at a base station in a wireless communication system includes generating a reference signal sequence, and mapping the reference signal sequence to resource elements (REs) included in one or more patterns for 8-port CSI-RS transmission among five patterns for 8-port CSI-RS transmission located in a first region of a PRB pair and three patterns for 8-port CSI-RS transmission located in a second region of the PRB pair. A maximum of two OFDM (orthogonal frequency division multiplexing) symbols is used for a physical downlink control channel in a subframe including the PRB pair.
US09503226B2
Disclosed is a method for efficiently managing base station retransmission traffic of a portable Internet system, and more particularly, a management method of traffic burst retransmission that can minimize a time required to retransmit a traffic burst by enhancing a hash node connection structure of a hash table.
US09503225B2
A terminal includes a determination unit that determines a PUCCH resource based on at least a first value in a case where downlink control information is detected with a PDCCH and a second value is not set, determines a PUCCH resource based on at least the second value in a case where the downlink control information is detected with the PDCCH and the second value is set, and determines the PUCCH resource based on at least the third value for the ePDCCH set with which the downlink control information is detected regardless of whether or not the second value is set in a case where the downlink control information is detected with the ePDCCH in the ePDCCH set. With this feature, a HARQ-ACK to a transport block transmitted on the PDSCH can be efficiently transmitted and received using a PUCCH.
US09503216B2
Systems and methods related to effective measurements in a cellular communications network are disclosed. In one embodiment, a network node obtains a reference measurement performed by a measuring node, where the reference measurement contains one or more interference components. The reference measurement may be, for instance, a reference signal quality measurement or a reference signal power measurement. The network node then mitigates at least one of the interference components contained in the reference measurement to thereby provide an effective measurement for the measuring node. In one embodiment, the network node mitigates the at least one interference component by obtaining a compensation value for mitigating the at least one interference component and applying the compensation value to the reference measurement to thereby provide the effective measurement.
US09503212B2
Provided is a station-side apparatus configured to conduct optical communication with a plurality of subscriber apparatuses via a plurality of wavelengths. The station-side apparatus includes a storage apparatus, management information stored in the storage apparatus and configured to indicate whether or not a subscriber apparatus is a first apparatus whose wavelength used for communication is changed to another wavelength, and a transmission unit configured to transmit downlink frames addressed to the plurality of subscriber apparatuses in an order of transmission determined based on the management information.
US09503209B2
Heterogeneous networks incorporate various small cells, such as femto cells and pico cells, in addition to a macro cell. Existing signals (e.g., PSS and SSS) configured as discovery reference signals (DRSs) may not be sufficient for a UE to discover different cells in a heterogeneous network. The disclosed aspects provide approaches for managing cell IDs for various DRS configurations to improve UE discovery of different cells in heterogeneous networks. In an aspect, a UE receives a first reference signal (e.g., based on a PCI) configured for performing a base station measurement by the UE. The UE further receives one or more second reference signals (e.g., based on a VCI which is associated with the PCI) configured for measurement by the UE. The UE performs the base station measurement based on the first reference signal and the one or more second reference signals.
US09503208B2
Base stations (BSs) can remove inter-BS interference components from received uplink signals using downlink information communicated over a backhaul network. The downlink information is associated with downlink transmissions of neighboring base stations, and is used to remove the inter-BS interference in accordance with interference cancellation techniques, e.g., signal interference cancellation (SIC), etc. The downlink information includes information associated with downlink transmission of the interfering BSs, such as information bits (e.g., data), parity information, control information, modulation and coding scheme (MCS) parameters, forward error correction (FEC) parameters, and other information. Additionally, inter-BS interference can be suppressed using channel information of interference channels using interference suppression techniques, e.g., interference rejection combining (IRC), etc.
US09503197B2
This spatial division multiplexing (SDM) in power-limited optical communication systems. In general, an SDM optical transmission system may be configured to increase data capacity over the data capacity of a non-SDM optical transmission system while maintaining power consumption at or below that of the existing non-SDM optical transmission system. To realize such an improvement in performance without increasing power consumption, an example SDM optical transmission may be constructed by reducing system bandwidth, reducing and/or altering equipment for filtering, reducing optical amplifier spacing, reducing operational amplifier power consumption, etc. In this manner, increased data transmission performance may be realized even where available power may be strictly limited.
US09503189B2
Aspects of the subject disclosure may include, for example, a system for determining a usage pattern, and sending instructions to a plurality of waveguide systems to transmit or receive electromagnetic waves along a surface of each of a plurality of wires according to the usage pattern. Other embodiments are disclosed.
US09503185B2
A controller at a distribution point (DP) of a communication system is coupled to a plurality of customer premises (CP) transceivers via drop connections in a point-to-multipoint architecture. Each drop connection is coupled to at least one switch that operates under the control of the controller for selectively isolating the drop connection from the controller, as well as the CP transceivers of other drop connections. In this regard, by controlling the states of the switches, the DP controller can control to which of the CP transceivers it is communicatively connected, and during operation the DP controller controls the switches such that it is communicatively connected only to the CP transceivers for which communication is desired or needed during a particular time interval.
US09503182B2
A method and system for reducing optical signal fading in an optical communication system include: dynamically obtaining turbulence-induced divergence and deviations of pointing direction for the atmosphere where an optical signal to be transmitted through; generating a single-transverse-mode laser beam of a predetermined diameter as the optical signal; dynamically varying the diameter of the laser beam to match the obtained turbulence-induced divergence of the atmosphere with a backtrack pointing direction; and transmitting the laser beam with varying diameter to a remote transceiver, as the optical signal.
US09503180B2
Presented herein are techniques for detection and avoidance of interference in a telecommunications network. In one example, a cable modem termination system (CMTS) is configured to receive upstream traffic from a plurality of cable modems. The CMTS detects collision characteristics resulting from substantially simultaneous transmissions from different combinations of the cable modems. Based on the detected collision characteristics, the CMTS designates/identifies collision groups for each of a plurality of the cable modems. After designation of the collision groups, the CMTS schedules upstream transmissions by the plurality of cable modems such that cable modems within the same collision group do not transmit within a same time frame and such that two or more cable modems that are not within the same collision group may transmit within a same time frame.
US09503179B2
A manner of providing redundancy protection for a data center network that is both reliable and low-cost. In a data center network where the data traffic between numerous access nodes and a network core layer via primary aggregation nodes, an optical network device such as and OLT (optical line terminal) is provided as a backup aggregation node for one or more of the primary aggregation nodes. When a communication path through a primary aggregation node fails, traffic is routed through the optical network device. In a preferred embodiment, a communication link is formed from a plurality of access nodes to a single port of the OLT or other optical network device via an optical splitter that combines upstream transmissions and distributes downstream transmissions. The upstream transmissions from the plurality of access nodes may occur according to an allocation schedule generated when the backup aggregation node is needed.
US09503178B2
The present description relates to an apparatus for transmitting wireless power and a method for same, comprising: a power transmission control portion for generating a packet comprising data for at least one electronic device; a modulation/demodulation portion for modulating a carrier signal so as to comprise the packet that is generated; and a power conversion portion for forming the wireless power signal for transmitting power, based on the carrier signal that is modulated, wherein the power transmission control portion transmits the packet to the at least one electronic device through the wireless power signal. Also, the present description relates to the electronic device and a method for receiving power by same, comprising: a power reception portion for receiving the wireless power signal from the apparatus for transmitting wireless power; a modulation/demodulation portion for demodulating the packet which is comprised in the wireless power signal; and a power reception control portion for obtaining data based on the packet that is demodulated.
US09503177B1
In disclosed examples, a satellite receiver dish (SRD) is peak aligned with a satellite in a geostationary orbit through use of guidance provided by a smartphone or tablet device fixedly attached to the SRD. A camera within the smartphone attached to the SRD can capture an image of a celestial object such as the sun. Celestial object data can be used to determine a predicted location of the sun at the time the image is captured. The predicted location of the sun can be used to determine an expected capture location of the sun within the captured image if the SRD was peak aligned with the satellite. A difference between the actual capture location of the sun and expected capture location of the sun within the capture image can be translated into at least one alignment adjustment for adjusting an azimuth position or an elevation position of the SRD.
US09503176B2
A communication system allows communication between two users separated by a long distance includes a source ground station, a constellation, one or more linking-gateways, and a destination ground station. The constellation includes groups of communication devices orbiting or traveling around the earth. A first communication device of a first group of communication devices is in communication with the source ground station and receives a communication from the source ground station. The linking-gateway is in communication with at least the first and a second group of communication devices. The linking-gateway receives the communication from the first group of communication devices and sends the communication to a second communication device of the second group of communication devices. The destination ground station is in communication with the second group of communication devices, the destination ground station receiving the communication from a communication device of the second group of communication devices.
US09503168B2
A method including using a precoding code book for controlling transmissions from four antennas of a device, said code book including a plurality of entries, wherein said entries are such that a single layer is mapped to each selected antenna, said code book entries including different antenna pair combinations whereby one or two antenna pairs are selected for transmission.
US09503159B2
An electronic device includes a processor, a memory, an embedded element storing information, and a short-range radio controller. The embedded element is readable by an external reader. The short-range radio controller is configured to receive a radio communication. If the short-range radio controller is being powered by a primary battery that powers the processor, the short-range radio controller is configured to route the radio communication to the embedded element if the radio communication is for accessing the embedded element, or route the radio communication to a component of the electronic device different from the embedded element if the radio communication is not for accessing the embedded element. If the short-range radio controller is not being powered by the primary battery, the short-range radio controller is configured to route the radio communication to the embedded element.
US09503157B2
Aspects of the present disclosure are directed toward receiver devices and methods of using receiver devices. One such method can include converting, using an analog-to-digital converter (ADC), and an analog input signal from power distribution lines that carry power using alternating current (AC) to a digital form. This input digital signal can be an oversampled digital signal, where the digital signal is oversampled relative to downstream processing (e.g., FFT-based processing). A processing circuit(s) can then be used to decimate the input digital signal according to a decimation rate. A reference signal can be generated by the processing circuit that is responsive to the decimation rate. The processing circuit can also be used to detect a change in a phase difference between the AC and reference signal and to modify, in response to detecting a change in the phase difference, the decimation rate to counteract the detected change in the phase difference.
US09503155B2
An integrated circuit including: an RF input/output; an on-chip digital interface including a plurality of IC pin connections wherein an output current from the on-chip digital interface is split into first and second parallel paths among the plurality of IC pin connections; first and second current sources; and a controller, wherein the controller is configured to determine a plurality of mutual inductances between the plurality of IC pin connections and the RF input/output; calculate a current ratio n based upon the plurality of mutual inductances between a first current driven on the first parallel path and a second current driven on the second parallel path; drive the first current source to produce the first current and the second current source to produce the second current wherein the first and second current have the determined ratio n; and measure a voltage at the RF input/output.
US09503151B2
A millimeter-wave radio frequency front-end circuit is provided. The front-end circuit comprises a millimeter-wave antenna configured to receive and transmit millimeter-wave signals; a matching network including at least a first inductor and a second inductor connected in parallel, wherein the matching network ensures impedance matching with the antenna when transmitting and receiving the millimeter wave signals; a power amplifier coupled to the antenna through the matching network; a low noise amplifier coupled to the antenna through the matching network, wherein the power amplifier is on and the low noise amplifier is off when transmitting the millimeter-wave signals, and the power amplifier is off and the low noise amplifier is on when receiving the millimeter-wave signals.
US09503149B1
An electronic device includes a transceiver including a transmitting interface and a receiving interface; a wireless network processor for transmitting or receiving wireless local area network signal; an antenna for transmitting or receiving the radio-frequency signal and transmitting or receiving the wireless local area network signal; an amplifier for amplifying the signal from the transmitting interface of the transceiver, the radio-frequency signal received from the antenna by the transceiver and the wireless local area network signal transmitted or received through the transmission interface by the wireless network processor; and a controller for controlling the amplifier to amplify the radio-frequency signal, or amplify the wireless local area network signal according to detection signals from the transceiver and the wireless network processor. The electronic device can reduce manufacturing costs and improve the connection performance of the wireless local area network.
US09503148B2
An integrated mobile phone protective case and carrier drawer system for securely containing small personal items, comprising: a regular mobile phone protective case portion; a drawer space integrally contained inside a rear part of the integrated mobile phone protective case; a drawer cover separate from the integrated mobile phone protective case, configured to mate onto the rear part of the integrated mobile phone protective case; a latching extension integrally affixed with the drawer cover; a latch integrally affixed with the integrated mobile phone protective case and configured to latch together with the latching extension; and a release actuator for releasing the latching extension from the latch; wherein: after the drawer cover has been slid onto the integrated mobile phone protective case, the latching extension simultaneously becomes latched together with the latch thereby preventing any personal items contained within the personal item carriage drawer from being removed from the drawer.
US09503147B2
A protective enclosure for an electronic device includes a cushioning layer and a structural layer. The cushioning layer covers the back surface and side surfaces of the installed electronic device. The structural layer is disposed over the cushioning layer and includes a back portion, a right side portion, and a left side portion. The structural layer includes a thinner region on the back portion. The thinner region has a thickness that is less than the thickness of the remainder of the back portion of the structural layer. The thinner region of the structural layer allows a section of the protective enclosure to bend away from the back surface of the electronic device during installation and removal of the electronic device from the protective enclosure.
US09503144B2
A band-type wireless communication device (10A) of an embodiment of the present invention is arranged such that a main body (1) contains an antenna (2) and a ground conductor (3) and that the ground conductor (3) is electrically connected to a metal section (5) on a first belt (4) joined with the main body (1).
US09503134B2
Certain aspects of the present disclosure relate to adapting transmitter configuration for efficient concurrent primary user detection through adaptive self-interference cancellation. A wireless transmitting device may schedule a transmission in a shared spectrum. The device may scan at least a portion of the shared spectrum during the transmission to receive a signal. Interference caused by the transmission may he cancelled from the received signal using self-interference cancellation circuitry. The device may determine whether the received signal indicates usage by a primary user of the shared spectrum. In an aspect, the transmission may be a SISO transmission. In another aspect, carrier aggregation may be used for the transmission and a potential carrier may be subject to primary user detection. The device may determine a self-interference cancellation complexity for a combination of carriers including the potential carrier, and may select one or more carriers for aggregation based on the self-interference cancellation complexity.
US09503133B2
A low noise detection system is disclosed in which a modulator located in a transmitter or a receiver is configured to convert a voltage data signal to a frequency signal, to modulate a baseband signal with the voltage data, and to output the modulated data signal. The receiver further includes a log detection amplifier configured to receive the modulated data signal and to regeneratively demodulate the modulated data signal to extract the data in an amplified analog data signal while not significantly amplifying any noise in the modulated data signal. The receiver further includes a digital conversion circuit for converting the amplified analog signal into a digital data signal.
US09503124B2
Provided is a method of decoding a low-density parity-check code (LDPC). The decoding method including an initialization process, a check node update process, a variable node update process, a tentative decoding process, and a parity check process, for a plurality of check nodes and a plurality of variable nodes, further includes detecting at least one inactive variable nodes that do not require variable node update among the variable nodes, the variable node update process is performed only on active variable nodes except for the inactive variable node, and the check node update process is performed without using the inactive variable node.
US09503122B1
A hardware data compressor. A first hardware engine scans an input block of characters and uses a plurality of lists of nodes to produce back pointers to matching strings in the input block to compress the input block. Each node points to a character in the input block previously scanned and has an associated probability that a back pointer to a matching string that begins with the pointed-to character will be produced by the first hardware engine. A second hardware engine, for each list of nodes of the plurality of lists, sorts the list according to the probabilities of the nodes in the list so that higher probability nodes appear earlier in the list for use by the first hardware engine to search for matching strings during the scan of the input block of characters.
US09503118B2
A multiplying analog to digital converter (ADC) including a successive-approximation-register (SAR) analog to digital converter (ADC) having a sample input and a feedback input and an ADC output configured with a feedback path configured to couple the ADC output to a digital to analog converter. A feedback attenuator is disposed in the feedback path, the feedback attenuator being configured to attenuate a feedback signal coupled to the feedback input, the feedback attenuator being configured to provide analog multiplication observed at the ADC output. A barrel shifter is configured to provide digital multiplication of the ADC output. The feedback attenuator may be configured as a divider network. The feedback attenuator may be configured to provide attenuation using only passive components. The feedback attenuator may be configured as a capacitive divider network. The feedback attenuator may be configured to provide attenuation ranging between 1 and 0.5.
US09503109B2
Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL's division value. The reset phase adjustment calculator can include a counter for counting a number of cycles of the reference clock signal since initialization of the fractional-N synthesizer, and the reset phase adjustment calculator can generate a phase adjustment signal based on the count. The synchronization circuit can synchronize the PLL in response to a synchronization signal, and can correct for a synchronization phase error indicated by the phase adjustment signal.
US09503103B2
A phase locked loop (PLL) circuit includes a frequency multiplier and a fractional-N type PLL. The clock output of the frequency multiplier is electrically connected to the clock input of the fractional-N type PLL. The loop bandwidth of the frequency multiplier of the PLL is smaller than the loop bandwidth of the fractional-N type PLL of the PLL.
US09503102B2
A system and method synchronizes multi-AWG system, where such systems are of a type having a master arbitrary waveform generator (AWG), one or more slave AWGs, and a sync hub having a sync controller and sync phase detector. The method operates by receiving at the sync hub a divided down clock (SystemRefClock) signal from a master arbitrary waveform generator (AWG). The method then derives a clock signal (SystemClock) from the SystemRefClock signal received from the master AWG and outputs the SystemClock signal to the master AWG and to the one or more slave AWGs Finally, the SystemClock signal is used to clock a synchronous trigger for the master AWG and one or more slave AWGs to play a waveform. In one aspect, the synchronous trigger includes AlignmentFiducial and Run signals to effect trigger and play commands.
US09503097B2
A circuit includes a magnetic logic unit including input terminals, output terminals, a field line, and magnetic tunnel junctions (MTJs). The field line electrically connects a first and a second input terminal, and is configured to generate a magnetic field based on an input to at least one of the first and the second input terminal. The input is based on a first analog input to the circuit. Each MTJ is electrically connected to a first and a second output terminal, and is configured such that an output of at least one of the first and the second output terminal varies in response to a combined resistance of the MTJs. The resistance of the MTJs varies based on the magnetic field. The circuit is configured to mix the first analog input and a second analog input to generate an analog output based on the output of the second output terminal.
US09503094B1
A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area in a second persona programming time. The device is configured to be controlled by a host to switch from running the first persona to running the second persona in a time less than the second persona programming time.
US09503091B2
Wordline decoder circuits for an embedded Multi-Time-Read-Only-Memory that includes a plurality of NMOS memory cells coupled to a plurality of wordlines in each row. The wordline decoder circuits control the charge trap behavior of the target NMOS memory array by the mode-dependent wordline high voltage (VWLH) and wordline low voltage (VWLL) trapping the charge in a programming mode by applying an elevated wordline voltage (EWLH) to one of the plurality of WLs, while de-trapping the charge in a reset mode by applying a negative wordline voltage (NWLL) to the entire array. The mode dependent voltage control is realized by switching to couple EWLH to VWLH in a programming mode, otherwise VDD to VWLH, while coupling NWLL to VWLL in a reset mode, otherwise, GND to VWLL. The switch includes plural gated diodes from VWLH with the wordline high protection voltage of VWLH_PR generated by lowering VWLH determined by gated diodes times threshold voltage. The switch includes a series of gated diodes from VWLL with a wordline low protection voltage of VWLL_PR generated by raising VWLL determined by the gated diodes by the threshold voltage, resulting in controlling the WL swing using thin-oxide devices.
US09503088B2
The invention provides a method for recovering NBTI/PBTI related parameter degradation in MOSFET devices. The method includes operating the at least one MOSFET device in a standby mode, exiting the at least one MOSFET device from the standby mode, holding the at least one MOSFET device in an active state for a predetermined time span after exiting the standby mode, and operating the at least one MOSFET device in an operational mode after the predetermined time span has elapsed.
US09503087B2
A programming element including a first transistor, a second transistor, and a capacitor between a logic circuit using a semiconductor element and a power supply is provided. In the programming element, a node where a drain electrode of the first transistor, a gate electrode of the second transistor, and one of electrodes of the capacitor are electrically connected to each other is formed. A potential can be supplied to each of a source electrode of the first transistor and the other of the electrodes of the capacitor. The power supply and the logic circuit are electrically connected to each other through a source electrode and a drain electrode of the second transistor. A connection state between the power supply and the logic circuit is controlled in accordance with the state of the second transistor.
US09503086B1
In an embodiment, an integrated circuit may include edge triggered flops that launch data to start a clock cycle and that capture data at the end of the clock cycle. Combinatorial logic circuitry may be coupled between the launching and capturing flops, and may be configured to operate on the launched data to generate result data for the capturing flops. One or more latches may be provided in the combinatorial logic circuitry, which may close and capture intermediate values responsive to an opposite edge of the clock than the edge that triggers the edge-triggered flops. In an embodiment, the clock to the latches may be gated with an enable. When the integrated circuit is not operating in the subthreshold voltage region, the enable may be in the disabled state. When operating in the subthreshold voltage region, the enable may be in the enabled state.
US09503080B2
A radio-frequency (RF) switch circuit is configured to maintain a disconnection or a connection between a node and an antenna terminal. The RF switch circuit comprises one or more switch cells. A switch cell comprises one or more transistors. The switch cell comprises one or more gate-drain capacitors. The switch cell comprises one or more source-drain capacitors. A gate-drain capacitor is coupled between a gate of a transistor and a drain of the transistor. A source-drain capacitor is coupled between a source of a transistor and a drain of the transistor.
US09503069B1
An apparatus includes first and second input transistors receiving respective first and second input signals, and a feedback circuit coupled to the first and second input transistors. The first and second input transistors provide first and second nodes with first and second currents according to values of the first and second input signals, respectively, when the feedback circuit is turned on. The first and second input transistors produce a reset value on the nodes when the feedback circuit is turned off. A method includes resetting, using first and second input transistors, respectively, values of first and second nodes to a reset value, providing first and second currents to the nodes using the first and second input transistors according to values of first and second input signals, and determining the values of the nodes according to the values of the first and second input signals.
US09503062B2
An example embodiment discloses a flip-flop including a first inverter configured to invert first data, first and second transistors connected to each other in series and configured to receive the inverted first data and a first clock, respectively, a third transistor and a first gate configured to perform a logic operation on the first data and the first clock, the third transistor configured to receive an output of the logic operation. The second transistor and the third transistor are connected to a first node.
US09503061B2
A system and method is disclosed for adaptively adjusting a duty cycle of a signal between a first and second chip in a 3D architecture/stack for adaptively calibrating a chip in a 3D architecture/stack. In one embodiment, the system includes a first chip and a second chip located within the 3D chip stack, wherein the first chip generates a calibration signal, the second chip receives the calibration signal and compares it to a reference signal to generate a comparison signal that further compared to a reference duty signal to generate a reference duty comparison signal, that is then provided to the first chip to generate a drive signal that adjusts a duty cycle of the calibration signal.
US09503056B2
One apparatus includes a notch filter that has a state observer unit and a parameter adaptation unit. The state observer unit is configured to receive a sampled noisy electrical signal and a sampled filtered electrical signal, the state observer unit having an estimated noise signal output, the estimated noise signal output carrying an estimated noise signal to be subtracted from the sampled noisy electrical signal, resulting in the filtered electrical signal. The parameter adaptation unit is configured to receive the estimated noise signal and an error signal from the state observer unit. The parameter adaptation unit is also configured to determine, based on the estimated noise signal and the error signal, an updated estimated noise frequency, thereby causing the state observer unit to generate an updated estimated noise signal to be provided on the estimated noise signal output.
US09503055B2
A signal processing apparatus that includes a circuit in which a signal processing function is performed during a first time period, the signal processing apparatus including or being associated with a switch or a filter in a power supply to the signal processing apparatus so as to disconnect the signal processing apparatus from the power supply or to filter the power supply during a second time period that is coincident with at least part of the first time period.
US09503048B2
To provide a small-sized piezoelectric vibrating reed and a piezoelectric vibrator with excellent durability. The piezoelectric vibrating reed includes a piezoelectric plate having a rectangular shape, a vibrating portion formed on a principal surface of the piezoelectric plate and a pair of mount portions for mounting the piezoelectric plate. The pair of mount portions are formed at both end portions of the piezoelectric plate in a longitudinal direction. The piezoelectric vibrator includes the piezoelectric vibrating reed and a package on which the mount portions of the piezoelectric vibrating reed are mounted.
US09503046B2
A MEMS or NEMS device with at least one component made of a non-naturally occurring isotope material. The refined isotopic material provides advantages to device operation such as reduced mechanical loss, increased breakdown voltage, improved tunability and other advantages.
US09503036B2
A power amplifier having a stack structure, including: a first driver stage that receives a power voltage from a power supply and receives and amplifies an input signal; a second driver stage that has a power input terminal connected with a ground terminal of the first driver stage and receiving a virtual power voltage and an input terminal connected with an output terminal of the first driver stage, and receives and amplifies an output signal from the first driver stage; and a power stage that receives the power voltage from the power supply, has an input terminal connected with an output terminal of the second driver stage, and receives and amplifies an output signal from the second driver stage.
US09503033B2
An audio amplifier is to transition between a power-down mode and an active mode, based on assertion and deassertion of a power down signal. A power down control module is to selectively assert and deassert the power down signal to the audio amplifier. The power down control module may identify at least one of a digital detection signal and an analog detection signal. The digital detection signal indicates the availability of a digital audio signal to be amplified, and the analog detection signal indicates the availability of an analog audio signal to be amplified.
US09503030B2
A radio frequency power amplifier comprises an input and output terminals, a main and peak amplifier stages, and an output power combiner for combining a main output signal and a peak output signal into an output signal. The output power combiner comprises a first combiner terminal electrically coupled to a main output terminal, a second combiner terminal electrically coupled to a peak output terminal, a first transition structure extending from the first combiner terminal in a first direction to a first end, a second transition structure extending from the second combiner terminal in the first direction to a second end, a first electrical conductor arranged between the first and the second ends, and a second electrical conductor arranged between the second combiner terminal and the output terminal. The first electrical conductor extends in a second direction perpendicular to the first direction. The second electrical conductor extends in the first direction.
US09503025B2
Aspects of this disclosure relate to efficient power amplifiers, such as class-F power amplifiers. A power amplifier transistor can provide an amplified RF signal. A termination can be coupled to an output of the power amplifier transistor and configured to provide a short circuit at a second harmonic. In some instances, the termination circuit can provide an open circuit at a third harmonic. A resonant circuit can be coupled to the output terminal of the power amplifier transistor and configured to provide an open circuit at the third harmonic. In certain embodiments, an input termination circuit coupled to an input terminal of the power amplifier transistor can provide a short circuit at the second harmonic. The power amplifiers of this disclosure can be implemented, for example, in envelope tracking applications.
US09503024B2
An amplifying device includes: a signal splitter configured to split an input signal to a plurality of signals having a phase difference between the plurality of signals fluctuating in accordance with an absolute value of an amplitude of the input signal; a plurality of amplifiers configured to amplify the plurality of signals respectively; a combiner configured to combine the amplified plurality of signals to generate an output signal; a selector configured to select one of output signals whose phase is inverted or non-inverted; and a switch controller configured to control the signal splitter so that phases of the plurality of signals are non-inverted, and to control the selector so that the selector selects one of the output signals, in accordance with a first point of time when the absolute value becomes a minimum or a second point of time deviated from the first point by a predetermined time period.
US09503021B2
An atomic oscillator includes an atom cell, a first light source device, a second light source device, and a reception section. The atom cell is filled with alkali metal. The first light source device emits a light beam that includes a resonance light beam pair configured to be circularly polarized with each other in the same direction and configured to cause the alkali metal to resonate. The second light source device emits a light beam that includes adjustment light beam configured to be circularly polarized in a reverse direction to the resonance light beam pair. The reception device receives the resonance light beam pair that pass through the atom cell. The adjustment light beam may include the resonance light beam that causes the alkali metal to resonate. In addition, the resonance light beam pair may be a line and the adjustment light beam is a line.
US09503015B2
A solar panel support comprising an upper coupling member including a hollow sleeve having a tapered inner surface increasing in diameter or cross-sectional dimension from the proximal end to the distal end having a key or wedge decreasing in width from the proximal end to the distal end projecting inwardly from the inner surface thereof and a lower support member including an elongated hollow pole or shaft having a slit or slot formed on the proximal end to receive the key or wedge therein such that when the elongated hollow pole or shaft is slidably received in the hollow sleeve and the key or wedge is aligned with the slit or slot the upper portion of the elongated hollow pole or shaft is squeezed by the hollow sleeve wedging the key within the slit or slot to secure the upper coupling member and lower support member together.
US09503011B2
The present invention is intended to reduce noise and vibration of a motor. A first duty correction circuit generates a first corrected duty instruction value which changes with an increment same as an increment of a duty instruction value and in which an offset value as a constant is reflected. A second duty correction circuit generates a second corrected duty instruction value which changes with an increment different from an increment of the duty instruction value. A selector outputs, as the corrected duty instruction value, either one of the first corrected duty instruction value and the second corrected duty instruction value in accordance with a magnitude relation between the duty instruction value and a duty reference value.
US09503010B2
An apparatus for minimizing an influence of a temperature change may include a motor, a temperature sensor for sensing a temperature of the motor to create the temperature information, a command compensation unit compensating a torque command or a magnetic flux demand according to the information on the sensed temperature to create a compensation torque command value or a compensation magnetic flux command value, and an inverter for driving the motor according to a D-axis voltage command value and a Q-axis voltage command value are created according to a D-axis current command value and a Q-axis current command value which are matched with the compensation torque command value or the compensation magnetic flux command value.
US09503000B2
A driving device of a multi-phase motor having a plurality of coils is provided. The driving device includes a back electromotive force (BEMF) detecting comparator connected to one of the plurality of coils to compare BEMF generated in one end of the one of the plurality of coils with a midpoint voltage of the plurality of coils and generate a BEMF detection signal, when the multi-phase motor starts to be driven; and an initial state detecting unit configured to detect a rotation state of the multi-phase motor based on the BEMF detection signal and a hall detection signal.
US09502979B2
An output switching circuit includes a switching circuit having a first transistor connected to a high-voltage power supply, a second transistor connected to a low-voltage power supply, and an output s terminal at a connection node between the first and second transistors; a comparison unit that compares an input signal with a feedback signal obtained by feedback of an output signal of the output terminal via a low-pass filter to generate a comparison signal; and a drive pulse generating unit that generates first drive pulses for driving the first transistor and second drive pulses for driving the second transistor in accordance with the comparison signal.
US09502977B2
A control apparatus (30) for a voltage converting apparatus controls a voltage converting apparatus (12) configured to realize one-arm drive by alternatively switching on first and second switching elements (Q1, Q2). The control apparatus for the voltage converting apparatus is provided with: a switching control signal generating device configured to generate switching control signals (PWI1, PWI2) for changing on and off the respective first and second switching elements; a current detecting device configured to detect a current value (IL) of a drive current flowing through the first or second switching element, at rise timing of the switching control signal, when the one-arm drive is changed between one-arm drive using the first arm and one-arm driving using the second arm; a current estimating device configured to estimate an average value of the drive current by using the detected current value; and a current controlling device configured to control the drive current on the basis of the estimated average value.
US09502969B2
A negative reference voltage generating circuit includes a switched capacitor circuit having a capacitor connected to a first and a second nodes, a first and a second switches connected to the first node, a third and a fourth switches connected to the second node; and a control circuit, generating a first to a fourth control signals to control the first to the fourth switches respectively. The control circuit applies a preset positive reference voltage to the first node to charge the capacitor during a first period, and outputs a negative voltage from the second node based on the voltage charged to the capacitor during a second period different from the first period. By repeating the first and the second periods, an inverting negative voltage of the positive reference voltage that is outputted from the second node is used as a negative reference voltage.
US09502962B2
Embodiments of the present application provide a power factor correction circuit and a power supply circuit. The power factor correction circuit includes a main correction circuit and a switch module. The main correction circuit includes: a first correction circuit and a second correction circuit that are configured to perform power factor correction on a forward alternating current voltage, and a third correction circuit and a fourth correction circuit that are configured to perform power factor correction on an inverse alternating current voltage. The switch module includes first switch units that are connected in parallel between an input terminal of the first correction circuit and an input terminal of the third correction circuit, and second switch units that are connected in parallel between an input terminal of the second correction circuit and an input terminal of the fourth correction circuit.
US09502952B2
A multi-phase motor including a rotor and a stator including at least one core. The stator includes a plurality of phase sections. Each phase section is configured to provide a phase of the multi-phase motor. Each phase section includes at least one of the core(s), at least two ring magnets having polarity facing in a substantially same direction, and a winding between the at least two ring magnets. The winding is configured to be energized to direct flux through the at least one core at a first portion associated with a first one of the ring magnets, and to be differently energized to direct flux through the at least one core at a second portion associated with a second one of the ring magnets.
US09502946B2
Provided is an inverter module for use in an inverter-integrated motor, the inverter module being arranged at an axial end portion of a motor, the inverter module including trapezoidal power modules, each of which has a single-phase inverter circuit mounted thereon, and includes an electrical connection terminal for a power supply arranged on a short side thereof and an electrical connection terminal for the motor arranged on a long side thereof. A plurality of the trapezoidal power modules are arranged in an annular pattern so that the long side of the each of the plurality of the trapezoidal power modules faces toward an outer periphery, to thereby construct a polyphase inverter circuit.
US09502944B2
An electric machine component includes a rotor assembly having a body provided with a number of pole members and a central hub. The body includes at least one mounting member projecting radially outwardly of the central hub. A fan member is mounted to the rotor. The fan member includes a hub portion and a number of fan blades projecting radially outwardly from the hub portion. The fan member includes at least one mounting element extending radially outwardly of the hub portion. The at least one mounting element is configured and disposed to engage with the at least one mounting member to radially and axially constrain the fan member to the rotor.
US09502904B2
A power conversion system includes a number of photovoltaic arrays, a number of inverters, a transformer, and processor. The processor is structured to control the number of inverters and operate the power conversion system to provide maximum efficiency of power conversion by the number of photovoltaic arrays, the number of inverters and the transformer, and to maximize power output from the number of photovoltaic arrays.
US09502902B2
For an array of installed energy harvesting devices, a method of gathering information about individual devices in the array and generating a layout or map of the installed devices based on the gathered information is provided. A communications gateway or a base station gathers the information and determines the positions of individual micro-inverters. The gathered information is used to generate a topological or geometrical map of the installed devices.
US09502899B2
Method and apparatus for controlling at least one generator and a Static Var Compensator (SVC) to improve dynamic performance of the power plant are provided. The method comprises: obtaining the required input parameters for control of said generators and SVC; determining a control mode of the generators and the SVC; calculating the control references based on the input parameters and the control mode of the generators and the SVC; and controlling the generators and/or the SVC according to the control references. The invention also relates to a corresponding apparatus which can implement the method of the invention.
US09502891B2
Provided is an ESD protection device that can suppress degradation of discharge characteristics caused by repeated discharge. The ESD protection device comprises (a) a ceramic multilayer substrate 12 in which a plurality of ceramic layers are stacked, (b) a cavity 13 formed inside the ceramic multilayer substrate 12, (c) at least one pair of discharge electrodes 14, 15 including opposing portions 14t, 15t that are formed along an inner surface of the cavity 13 and that face each other with a spacing held therebetween, and (d) outer electrodes formed on a surface of the ceramic multilayer substrate 12 and connected to the discharge electrodes 14, 15. At least one of the opposing portions 14t, 15t of the discharge electrodes 14, 15 is connected to one end portion of a via conductor 22, 23 penetrating through the ceramic layer of the ceramic multilayer substrate 12.
US09502890B2
Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a first base region of semiconductor material having a first conductivity type, a second base region of semiconductor material having the first conductivity type and a dopant concentration that is less than the first base region, a third base region of semiconductor material having the first conductivity type and a dopant concentration that is greater than the second base region, an emitter region of semiconductor material having a second conductivity type opposite the first conductivity type within the first base region, and a collector region of semiconductor material having the second conductivity type. At least a portion of the second base region resides between the third base region and the first base region and at least a portion of the first base region resides between the emitter region and the collector region.
US09502881B2
An embodiment of the invention relates to a switchgear which includes a control unit, a supply connection and a first current path. The first current path includes a first electromechanical switch and, connected in series to the first switch, a parallel connection of a second electromechanical switch to a semiconductor switch. The switchgear includes an energy accumulator and a measuring device. A control unit is capable of monitoring energy supply coming in through the supply connection. If the energy supply through the supply connection reaches a critical range, the control unit controls the output of the switching signals via the energy of the energy accumulator such that: in a first step, the semiconductor switch is switched to be electrically conducting and the second switch is then opened, and in a second step, the semiconductor switch is switched to be electrically non-conducting and the second switch is then opened.
US09502880B2
Methods and systems to detect and control plasma fires are disclosed. An example method includes monitoring an optical fiber using a sensor, the optical fiber being positioned proximate a conductor through which electricity is to flow, the optical fiber not being coupled to a signal generator or a light source; identifying a change in the optical fiber, the change associated with a change in the optical fiber or a casing surrounding the optical fiber due to a plasma fire; and controlling the flow of electricity through the conductor based on identifying the change.
US09502878B2
An enclosure (20, 220) includes a housing (22, 222) and a sealing unit (48, 42a, 232) that mounts within a sealing unit opening (28, 230) of the housing. The sealing unit (48, 42a, 232) provides a peripheral seal between the housing (22, 222) and the sealing unit (48, 42a, 232) and provides seals around cable ports (50). The sealing unit (48, 42a, 232) can be mounted to and removed from the housing (222) through the sealing unit opening (28, 230). The base (26) lacks a permanent retention structure (55, 155a) at the outer end of the base (26) for retaining the sealing unit (48, 42a, 232) in the base (26). A cover (24) is removable from the base (26) without requiring the sealant arrangement (52, 236) to be de-pressurized. A fastening arrangement (55, 155a) releasably retains the sealing unit (48, 42a, 232) in the sealing unit opening (28, 230).
US09502865B2
An igniter (20) includes an outer insulator (24) formed of an outer ceramic material hermetically sealed to a conductive core (26). The conductive core (26) is formed of a core ceramic material and a conductive component, such as an electrically conductive coating applied to the core ceramic material or metal particles or wires embedded in the core ceramic material. The conductive core (26) is typically sintered and disposed in the green outer insulator (24). The components are then sintered together such that the outer insulator (24) shrinks onto the conductive core (26) and the hermetic seal forms therebetween. The conductive core (26) fills the outer insulator (24), so that the conductive core (26) is disposed at an insulator nose end (34) of the outer insulator (24) and the electrical discharge (22) can be emitted from the conductive core (26), eliminating the need for a separate firing tip.
US09502860B1
A tunable swept multi-laser system comprising a first laser source, a second laser source, a first wavelength blocking component, and a second wavelength blocking component. The first laser source has a first wavelength working range and the second laser source has a second wavelength working range. The first wavelength working range begins at a first start wavelength and ends at a first end wavelength. The second wavelength working range begins at a second start wavelength, ends at a second end wavelength, and overlaps with the first wavelength working range. The first wavelength blocking component has a first wavelength blocking range including the first end wavelength. The second wavelength blocking component has a second wavelength blocking range including the second start wavelength. The first wavelength blocking component is optically coupled with the first laser source and the second wavelength blocking component is optically coupled with the second laser source.
US09502851B1
An apparatus includes a polymer waveguide having a doped region, with amplifying dopant, separating a first un-doped region and a second un-doped region. The doped region being doped with an amplifying dopant. An optical pump source illuminates the doped region to allow light to transmit from the first un-doped region to the second un-doped region.
US09502841B2
A plug for provision of power includes a housing forming a receiving cavity with two opposite sites in a vertical direction which is compatible with a standard plug connector with twelve contacts on each site and a first and second rows of contacts on the sides while in diagonally symmetrical manner. Each contact includes a contacting section, and a connecting section for directly connecting to a corresponding wire. Each row of contacts is categorized with a pair of power contacts, a pair of grounding contacts and a specific contact without any high speed differential pair. Two pair of power contacts of both two rows are electrically connected together either via direct mechanical connection via vertical extensions or via indirect electrical connection via the latch which has a pair of side arms extending into the receiving cavity at two opposite transverse ends.
US09502824B2
An electrical connector for terminating an electrical cable and for engaging with a mating electrical connector comprises a body, resilient member, and a collar. The body has an engagement portion including a sleeve which extends in a longitudinal direction for engaging with the mating electrical connector. The sleeve comprises a keyway configured to receive a keyed mating connector. The resilient member is arranged on the sleeve and can deform in a transverse direction perpendicular to the direction and provide a reaction force for maintaining the engagement of the connector with the mating connector. The collar is configured to rotate about the sleeve, and comprises a radially inwardly protruding pin which extends into the sleeve and can be moved between two positions. One position is within the keyway between the key of the mating connector and the keyway opening such that the pin prevents axial disengagement of the connector.
US09502808B1
An electrical receptacle including a body having a plurality of electrical connections a device face connected to the body, wherein the device face is slidable with respect to the body. An electrical device including a body having a face, a locking mechanism positioned within the body, and wherein the locking mechanism interacts with an electrical plug when the face is slide to a locked position.
US09502803B2
A terminal and an electrical connector are shown and the terminal has a tail, an elastic arm, a contact and a front guiding member. The elastic arm is connected to the tail. The contact is positioned at a distal end of the elastic arm. The contact has a front guiding surface extending forwards and downwards. The front guiding member extends forwards from the elastic arm. The front guiding member has a front guiding portion that extends forwards and downwards. An extending direction of the elastic arm and an extending direction of the front guiding member intersected at an angle. The front guiding portion is positioned in front of the front guiding surface of the contact.
US09502798B1
An electrical connector having a circuit board and elastic pieces is provided. The elastic pieces are disposed on the circuit board. Each elastic piece includes contact portions, fixing portions and insulating portions. The fixing portions are fixed on the circuit board and electrically connected to the circuit board. The contact portions are connected to corresponding fixing portions and are protruded from the fixing portions along a direction away from the circuit board. Each insulating portion is connected to two adjacent fixing portions, so as to connect and electrically insulate the fixing portions. Moreover, an electronic device including the above-mentioned connector is also provided.
US09502796B2
A round plug-in connector has a connection side configured for contacting circuit boards. For transmitting several independent, differential signals, the plug-in connector includes electric contacts arranged in pairs, with each of four signal pairs being insulated from each other by a cruciform structure, and being arranged inside an electrically non-conductive round body surrounding the cruciform structure. An electrically conductive screen cross is surrounded by a cruciform contact carrier with accepting grooves in diagonally embodied internal edges for holding the electric contacts. The round body is pushed over the cruciform arrangement, and is surrounded by an electrically conductive housing. Connection ends of the electric contacts that are intended to be aligned precisely on a circuit board, via a positioning aid, are attached to the round body. The positioning aid includes respective bore holes for the connection ends of the electric contacts, which coincide with soldered bore holes on the circuit board.
US09502760B2
An antenna section is housed in a housing space which is defined by a radome and a housing, and provided with a transmitting antenna that transmits radar waves composed of radio waves of a predetermined frequency and a receiving antenna that receives the radar waves. The radome has a transmission section that is a portion transmitting the radar waves and an attenuation section that is a portion attenuating the radar waves. The attenuation section includes a first attenuation layer formed of a material for attenuating the radar waves. The first attenuation layer has a thickness that is 2n−1 times (n is a natural number) of one-quarter of a wavelength of the radar waves in the first attenuation layer.
US09502751B2
Disclosed is an antenna system and method to design a desensitized antenna element. The system and method are operative to design a configuration of an antenna to overcome a number of operational conditions in which the frequency response of the antenna element may be uniquely or significantly detuned or offset or in which undesired noise, signal interference, or electromagnetic coupling effects may affect or be induced by the antenna element. These operational conditions may include the presence of any combination of user body parts, conductive materials, or dielectric materials as well as neighboring electronic systems or other sources of undesired noise, signal interference, and electromagnetic coupling. The system is designed to mitigate adverse effects, when operating in a potentially antenna-detuning environment or under conditions that may affect other systems or be susceptible to being affected by other sources, by using a desensitizer element comprising at least one electrical circuit component.
US09502750B2
An electronic device may have an antenna for providing coverage in wireless communications bands of interest. The wireless communications bands may include a communications band at a first frequency. The antenna may have a parasitic antenna resonating element that supports a low efficiency resonance. In response to operation of the electronic device in free space, the low efficiency resonance will be located at a second frequency that is greater than the first frequency. In response to operation of the electronic device in proximity to a user's body or other external object, the antenna will be loaded and the low efficiency resonance associated with the parasitic antenna resonating element will shift to the communications band at the first frequency. The antenna may include a resonating element formed on a flexible printed circuit or a dielectric carrier such as a plastic support structure.
US09502747B2
In an example embodiment, an airborne radio frequency (RF) antenna device can comprise: a radiating portion; a waveguide portion connected to the radiating portion; a desiccant airflow channel; and an internal air volume located within the RF antenna device and associated with the desiccant airflow channel. The desiccant airflow channel can be integral with the RF antenna device. The internal air volume can be vented to the environment outside of the RF antenna device through the desiccant airflow channel.
US09502746B2
A 180° hybrid coupler includes three coupled-line couplers connected between two inputs and two outputs. Each of the three coupled-line couplers is defined by at least one ground conductor and only two signal conductors.
US09502743B2
Various embodiments provide for waveguide assemblies which may be utilized in wireless communication systems. Various embodiments may allow for waveguide assemblies to be assembled using tools and methodologies that are simpler than the conventional alternatives. Some embodiments provide for a waveguide assembly that comprises a straight tubular portion configured to be shortened, using simple techniques and tools, in order to fit into a waveguide assembly. For instance, for some embodiments, the waveguide assembly may be configured such that the straight portion can be shortened, at a cross section of the portion, using a basic cutting tool, such a hacksaw. In some embodiments, the straight portion may be further configured such that regardless of whether the straight tubular portion is shortened, the waveguide assembly remains capable of coupling to flanges, which facilitate coupling the straight tubular portion to connectable assemblies, such as other waveguide assemblies, radio equipment, or antennas.
US09502741B2
An air battery for use by being stacked in a battery pack has a cathode constituting member and an anode material adapted such that at least a part of the anode material is brought into direct contact with a cathode constituting member of another air battery. In this configuration, it is possible to eliminate the need to use an anode cap for sealing on the anode side and thereby possible to achieve not only reduction in weight and size but also reduction in cost.
US09502739B2
A battery pack is disclosed. One aspect includes a battery pack module having a housing and a plurality of battery packs, each pack housing a case in which a plurality of batteries are received, an electrode tab to connect the batteries to form one unit, and a data wire having a first end connected to the electrode tab, to act as a signal transmitting line of the plurality of batteries.
US09502721B2
Methods for fabricating an interconnect for a fuel cell system that include forming a metal powder into a preform structure, positioning the preform structure in a die cavity of a press apparatus, and compressing the preform structure in the press apparatus to form the interconnect. Further embodiments include use of thin inserts in the die cavity to provide reduced permeability and/or including filler material in the die cavity.
US09502703B2
A laminated microporous film including a base which is formed from a non-woven fabric, and a surface layer which is formed on at least one of the surfaces of the base and includes a resin material and inorganic particles, wherein variation in thickness which is expressed using a standard deviation is equal to or less than 2.5%.
US09502701B1
An electronic device includes a battery module, a casing and a latching mechanism. The battery module has at least one battery retention tab. A battery compartment is formed on the casing. The battery module is detachably installed in the battery compartment, and the casing has a stopping structure. The latching mechanism is slidably installed on the casing and includes a latching cover, a lock member and a resilient member. The latching cover is installed on the casing in a slidable manner. The lock member is pivoted to the latching cover. The resilient member is installed on the latching cover. When the latching cover slides to the lock position, the resilient member forces the lock member to engage with the stopping structure, so as to fix the latching cover in the lock position.
US09502700B2
A power train battery assembly of an electric, fuel-cell or hybrid vehicle, said assembly having a plurality of battery cells (16), each encased in an individual and externally-closed cell housing (18), that are combined into a cell stack and moreover having at least one pipe (36) conducting cooling fluid for the removal of heat energy from the battery cells (16). At least one heat-conducting fin (42) that originates from the pipe (36) flatly abuts, at least in sections, at least one cell housing (18).
US09502690B2
A highly reliable light-emitting device which includes an organic EL element and is lightweight is provided. The light-emitting device includes a first organic resin layer; a first glass layer over the first organic resin layer; a light-emitting element over the first glass layer; a second glass layer over the light-emitting element; and a second organic resin layer over the second glass layer. The first organic resin layer and the first glass layer each have a property of transmitting visible light. The light-emitting element includes a first electrode having a property of transmitting visible light, a layer containing a light-emitting organic compound, and a second electrode stacked in this order from the first glass layer side.
US09502688B2
Provided are an organic light emitting display apparatus and a method of manufacturing the same. The organic light emitting display apparatus includes: a thin film transistor (TFT) substrate including a plurality of thin film transistors, an organic light-emissive device on the TFT substrate, and an encapsulation layer on the TFT substrate and the organic light-emissive device, the encapsulation layer being configured to cover the organic light-emissive device, the encapsulation layer including a hybrid material including: a block copolymer, and functionalized graphene.
US09502677B2
The present invention relates to an organic light emitting display device. An aspect of the present invention provides an organic light emitting display device comprising a first electrode on a substrate, an organic light emitting layer on the substrate, and a second electrode including at least two layers of which a composition of compensation materials is different on the organic light emitting layer.
US09502675B2
Methods for passivating a nanotube fabric layer within a nanotube switching device to prevent or otherwise limit the encroachment of an adjacent material layer are disclosed. In some embodiments, a sacrificial material is implanted within a porous nanotube fabric layer to fill in the voids within the porous nanotube fabric layer while one or more other material layers are applied adjacent to the nanotube fabric layer. Once the other material layers are in place, the sacrificial material is removed. In other embodiments, a non-sacrificial filler material (selected and deposited in such a way as to not impair the switching function of the nanotube fabric layer) is used to form a barrier layer within a nanotube fabric layer. In other embodiments, individual nanotube elements are combined with and nanoscopic particles to limit the porosity of a nanotube fabric layer.
US09502669B2
The present specification relates to an organic light emitting diode.
US09502667B2
A nitrogen-containing heterocyclic compound wherein a pyrrole ring, an aromatic ring and a 7-membered ring are fused one another, a material for organic electroluminescence device including the compound, and an organic electroluminescence device including the material.
US09502666B2
A light-emitting element emitting phosphorescence and having high emission efficiency, in which a property of injecting holes to a light-emitting layer is increased, is provided. The light-emitting layer of the light-emitting element includes a first organic compound represented by the following general formula (G1) and a second organic compound which is a phosphorescent compound. The difference between the HOMO level of the first organic compound and the HOMO level of the second organic compound is lower than or equal to 0.3 eV.
US09502662B2
Disclosed are a compound for an organic optoelectronic device, an organic light emitting diode including the same, and a display device including the organic light emitting diode. The compound for an organic optoelectronic device represented by the following Chemical Formula ad-1 provides an organic light emitting diode having life-span characteristics due to excellent electrochemical and thermal stability, and high luminous efficiency at a low driving voltage.
US09502656B2
The present disclosure provides novel compounds based on azadibenzothiophenes, azadibenzofurans and azadibenzoselenophenes with at least two nitrogen atoms in the aza rings. The compounds can be used in green, red, yellow and white emitting devices as electron-transporting hosts.
US09502643B2
A method of fabricating a semiconductor device includes forming conductive pillars on a substrate, sequentially forming a sacrificial layer and a molding structure between the conductive pillars, forming a conductive layer on the molding structure, such that the conductive layer is connected to the conductive pillars, removing the sacrificial layer to form an air gap, removing the molding structure to form an expanded air gap, and patterning the conductive layer to open the expanded air gap.
US09502642B2
A method used while forming a magnetic tunnel junction comprises forming non-magnetic tunnel insulator material over magnetic electrode material. The tunnel insulator material comprises MgO and the magnetic electrode material comprises Co and Fe. B is proximate opposing facing surfaces of the tunnel insulator material and the magnetic electrode material. B-absorbing material is formed over a sidewall of at least one of the magnetic electrode material and the tunnel insulator material. B is absorbed from proximate the opposing facing surfaces laterally into the B-absorbing material. Other embodiments are disclosed, including magnetic tunnel junctions independent of method of manufacture.
US09502623B1
A light emitting device includes a base structure, a wall, a light emitting element, a protection element, and a light reflective portion. The wall includes an inner peripheral surface defining an opening. The opening has a substantially polygonal shape in a planar view of the light emitting device. The light reflective portion has a maximum length which is longest in the light reflective portion. The maximum length is defined at a maximum-length position closest to the first corner among a plurality of positions defined in the light reflective portion. The light reflective portion has a minimum length which is shortest in the light reflective portion. The minimum length is defined at a minimum-length position arranged apart from the maximum-length position. The light reflective portion includes an inclined surface extending from the maximum-length position to the minimum-length position.
US09502611B2
The invention concerns an optoelectronic component comprising a layer structure with a light-active layer. In a first lateral region the light-active layer has a higher density of V-defects than in a second lateral region.
US09502610B2
A method for manufacturing a light emitting device, includes a first step of mounting a light emitting element on a support base with a bump; and a second step of clamping the support base and the light emitting element and pressing between a lower molding die and an upper molding die to plastically deform the bump, and injecting the compound of a cover member into a mold cavity between the lower molding die and the upper molding die and curing the compound to form the cover member that covers at least a lower surface of the light emitting element after the first step.
US09502603B2
Vertically structured group III nitride semiconductor LED chip and method for manufacturing the same
A method for manufacturing a vertically structured Group III nitride semiconductor LED chip includes a first step of forming a light emitting structure laminate; a second step of forming a plurality of separate light emitting structures by partially removing the light emitting structure laminate to partially expose the growth substrate; a third step of forming a conductive support, which conductive support integrally supporting the light emitting structures; a fourth step of separating the growth substrate by removing the lift-off layer; and a fifth step of dividing the conductive support between the light emitting structures thereby singulating a plurality of LED chips each having the light emitting structure. A first through-hole is formed to open in a central region of each of the light emitting structures such that at least the lift-off layer is exposed, and an etchant is supplied from the first through-hole in the fourth step.
US09502601B1
Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell can include a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed over an exposed outer portion of the first polycrystalline silicon emitter region and is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region. Metallization methods, include etching techniques for forming a first and second conductive contact structure are also described.
US09502600B2
A solution for forming at least a portion of an active layer of an electronic or electro-optic device includes a solvent, an additive mixed with the solvent to provide a solvent-additive blend, and a solute that includes at least one of a transition metal, an alkali metal, an alkaline earth metal, Al, Ga, In, Ge, Sn, or Sb dissolved in elemental form in the solvent-additive blend. The additive is selected from the group of additives consisting of NR1R2NHCOOH, NH2N—HCONHNH2, NH2COOH.NH3, NH2NHC(═NH)NH2.H2CO3, NH2NHCSNHNH2, NH2NHCSSH and all combinations thereof. R1 and R2 are each independently selected from hydrogen, aryl, methyl, ethyl and a linear, branched or cyclic alkyl of 3-6 carbon atoms. Methods of producing the solution, a method of producing a Kesterite film on a substructure and devices made with the solutions and methods are also provided.
US09502591B2
Disclosed is a solar cell apparatus. The solar cell apparatus include: a substrate; a back electrode layer on the substrate; a light absorbing layer on the back electrode layer; a window layer on the light absorbing layer; and a bus bar provided beside the light absorbing layer, the bus bar being connected to the back electrode layer.
US09502586B1
A symmetric varactor structure may include a first varactor component. The first varactor component may include a gate operating as a second plate, a gate oxide layer operating as a dielectric layer and a body operating as a first plate of an area modulating capacitor. In addition, doped regions may surround the body of the first varactor component. The first varactor component may be supported on a backside by an isolation layer. The symmetric varactor structure may also include a second varactor component electrically coupled to the backside of the first varactor component through a backside conductive layer.
US09502585B2
A method of manufacturing a Schottky barrier diode is provided, which includes: providing a semiconductor substrate including a first well region of a first conductivity type in the semiconductor substrate; forming a surface-doped layer having a dopant of a second conductivity type opposite to the first conductivity type in the first well region; forming a dielectric layer in contact with the surface-doped layer; performing a thermal treatment on the surface-doped layer to move the dopant of the surface-doped layer in the dielectric layer; removing the dielectric layer to expose the first well region; and forming a silicide layer in contact with the exposed first well region. A Schottky barrier diode is also provided.
US09502582B2
A non-volatile memory unit includes a substrate, a first dielectric layer, an erase gate, a floating gate, a second dielectric layer, a coupled dielectric layer and a couple control gate. The substrate has a source region and a drain region, and the first dielectric layer is formed on the substrate. The erase gate, the floating gate, the second dielectric layer and the selective gate are formed on the first dielectric layer. The second dielectric layer and coupled dielectric layer are formed among and above the erase gate, the floating gate and the selective gate, and the couple control gate is formed on the coupled dielectric layer.
US09502576B2
There are provided a thin film transistor and a manufacturing method thereof, an array substrate and a display device. The thin film transistor is formed on a base substrate, and includes a gate electrode, an active layer, a source electrode and a drain electrode, the gate electrode includes a first section, a second section and a third section, the first section and the third section correspond to locations of the source electrode and the drain electrode, respectively; the base substrate has two recesses formed therein, and the first section and the third section are situated in the two recesses, respectively; the first section and the third section are covered with a filling layer; the filling layer and the second section are covered with a gate insulating layer, the active layer, the source electrode and the drain electrode in sequence.
US09502568B2
Techniques are disclosed for forming a non-planar quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), and a quantum well layer. A fin structure is formed in the quantum well structure, and an interfacial layer provided over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
US09502565B2
A circuit device having differently-strained NMOS and PMOS FinFETs is provided. In an exemplary embodiment, a semiconductor device includes a substrate with a first fin structure and a second fin structure formed thereup. The first fin structure includes opposing source/drain regions disposed above a surface of the substrate; a channel region disposed between the opposing source/drain regions and disposed above the surface of the substrate; and a first buried layer disposed between the channel region and the substrate. The first buried layer includes a compound semiconductor oxide. The second fin structure includes a second buried layer disposed between the substrate and a channel region of the second fin structure, such that the second buried layer is different in composition from the first. For example, the second fin structure may be free of the compound semiconductor oxide.
US09502562B2
Fin mask structures are formed over a semiconductor material portion on a crystalline insulator layer. A disposable gate structure and a gate spacer are formed over the fin mask structures. Employing the disposable gate structure and the gate spacer as an etch mask, physically exposed portions of the fin mask structures and the semiconductor material portion are removed by an etch. A source region and a drain region are formed by selective epitaxy of a semiconductor material from physically exposed surfaces of the crystalline insulator layer. The disposable gate structure is removed selective to the source region and the drain region. Semiconductor fins are formed by anisotropically etching portions of the semiconductor material portion, employing the gate spacer and the fin mask structures as etch masks. A gate dielectric and a gate electrode are formed within the gate cavity.
US09502559B2
The present disclosure relates to method of forming a transistor device having epitaxial source and drain regions with dislocation stress memorization (DSM) regions that provide stress to an epitaxial channel region, and an associated device. The method forms a first dislocation stress memorization (DSM) region and a second DSM region having stressed lattices within a substrate. The substrate is selectively etched to form a source cavity and a drain cavity extending from an upper surface of the substrate to positions contacting the first DSM region and the second DSM region. An epitaxial source is formed within the source cavity and an epitaxial drain region is formed within the drain cavity. A gate structure is formed over the substrate at a location laterally between the epitaxial source region and the epitaxial drain region.
US09502557B2
An LDMOSFET is designed with dual modes. At the high voltage mode, it supports a high breakdown voltage and is biased at a high voltage to get the benefits of high output power, higher output impedance and lower matching loss. At the low voltage mode, it exhibits a reduced knee voltage so that some extra voltage and power can be gained although it is biased at lower voltage. The efficiency is therefore improved as well.
US09502547B2
An IGBT device may be formed from a substrate including a bottom semiconductor layer of a first conductivity and an upper semiconductor layer of a second conductivity type located above the bottom semiconductor layer. Trenches for trench gates are formed in the substrate. Each trench extends vertically into the upper semiconductor layer and is provided with a gate insulator on each side of the trench and is filled with polysilicon. A first conductivity type floating body region is formed between two neighboring trenches and over the substrate. A bottom of the floating body region is close in depth to but above a bottom of the polysilicon in the trench. A heavily doped second conductivity type top region is formed over the floating body region. A first conductivity type body region is formed over the top region. The floating body region has a lower doping concentration than the body region.
US09502546B2
A semiconductor device and manufacturing method achieve miniaturization, prevent rise in threshold voltage and on-state voltage, and prevent decrease in breakdown resistance. N+-type emitter region and p++-type contact region are repeatedly alternately disposed in a first direction in which a trench extends in stripe form in a mesa portion sandwiched between trench gates. P+-type region covers an end portion on lower side of junction interface between n+-type emitter region and p++-type contact region. Formation of trench gate structure is such that n+-type emitter region is selectively formed at predetermined intervals in the first direction in the mesa portion by first ion implantation. P+-type region is formed less deeply than n+-type emitter region in the entire mesa portion by second ion implantation. The p++-type contact region is selectively formed inside the p+-type region by third ion implantation. N+-type emitter region and p++-type contact region are diffused and brought into contact.
US09502543B1
Methods of fabricating a memory device are described. Generally, the method begins with forming a tunnel dielectric layer over a channel region formed from a silicon containing layer over a surface of a substrate. A first oxygen-rich nitride layer of a multi-layer charge-trapping region is formed on a surface of the tunnel dielectric layer, and a second oxygen-lean nitride layer formed over the first nitride layer. A blocking dielectric layer is formed over a surface of the second layer of the multi-layer charge-trapping region, and a high work function gate electrode upon over the blocking dielectric layer. Other embodiments are also described.
US09502541B2
A fin structure for a fin field effect transistor (FinFET) device is provided. The device includes a substrate, a first semiconductor material disposed on the substrate, a shallow trench isolation (STI) region disposed over the substrate and formed on opposing sides of the first semiconductor material, and a second semiconductor material forming a first fin and a second fin disposed on the STI region, the first fin spaced apart from the second fin by a width of the first semiconductor material. The fin structure may be used to generate the FinFET device by forming a gate layer formed over the first fin, a top surface of the first semiconductor material disposed between the first and second fins, and the second fin.
US09502538B2
A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device also includes a gate stack covering a portion of the fin structure and an epitaxially grown source/drain structure over the fin structure and adjacent to the gate stack. The semiconductor device further includes a semiconductor protection layer over the epitaxially grown source/drain structure. The semiconductor protection layer has an atomic concentration of carbon greater than that of the epitaxially grown source/drain structure.
US09502532B2
Provided is a method of manufacturing a semiconductor device including: forming a gate electrode structure on an active region of a semiconductor substrate; forming recesses in regions positioned on both sides of the gate electrode structure on the active region; performing a pre-treatment on the recesses using an inert gas plasma; growing epitaxial layers for a source and a drain on the pre-treated recesses; and forming a source electrode structure and a drain electrode structure in the epitaxial layers for the source and the drain, respectively. Also provided is a method in which, after an etching process for forming recesses and/or after an etching process for forming a contact hole, an etched surface may be treated with an inert gas plasma before growing an epitaxial layer. Thus, one or two types of plasma treatment may be employed in the method.
US09502517B2
A display device, an array substrate and a fabrication method thereof are provided. The array substrate comprises a data line and a gate line, the data line and the gate line intersect with each other to define a pixel region. The pixel region comprises a first thin film transistor and a pixel electrode. The fabrication method comprises: forming an active layer film and a source-drain metal layer on a substrate, and forming an active layer, a source electrode and a drain electrode of the first thin film transistor on the substrate by a single patterning process.
US09502516B2
Recessed access transistor devices used with semiconductor devices may include gate electrodes having materials with multiple work functions, materials that are electrically isolated from each other and supplied with two or more voltage supplies, or materials that create a diode junction within the gate electrode.
US09502513B2
This disclosure discloses a non-volatile memory component and a manufacture method of the same. The non-volatile memory component includes a substrate, a first dielectric layer on the substrate, an erase gate (EG), a floating gate (FG) and a select gate (EG). The substrate includes a source region and a drain region. The erase gate (EG), the floating gate (FG) and the select gate (EG) are formed on the first dielectric layer. Additionally, non-volatile memory component includes a coupling dielectric layer formed in the intervals and the upper region of the erase gate (EG), the floating gate (FG) and the select gate (SG), and a coupling gate (CG) formed on the coupling dielectric layer.
US09502501B2
A lateral field effect transistor device has a plurality of source and drain cells. Each source cell has a central semiconductor source region, and each drain cell has a central semiconductor drain region. The device has a first metallic conductive path which extends from a source electrode to join the source regions, thereby connecting the source cells in series to the source electrode. The device has a second metallic conductive path which extends from a drain electrode to join the drain regions, thereby connecting the drain cells in series to the drain electrode. The device has a gate path which extends from a gate electrode around the edges of the cells to form boundaries between neighboring source and drain cells, thereby forming respective field effect transistors between the source and drain regions of neighboring cells. The source cells and drain cells tessellate to cover an area of the device.
US09502499B2
A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first trench between a first active region and a second active region of the substrate. The semiconductor device structure includes an isolation structure in the first trench. The isolation structure includes a liner layer, an insulating layer, and an isolation layer. The liner layer covers an inner wall and a bottom surface of the first trench. The insulating layer covers the liner layer and has a second trench in the first trench. The isolation layer is over the insulating layer and fills the second trench. A first thickness of the insulating layer is greater than a second thickness of the liner layer.
US09502495B2
A semiconductor device according to the present invention includes a semiconductor layer provided with a gate trench, a first conductivity type source region formed to be exposed on a surface side of the semiconductor layer, a second conductivity type channel region formed on a side of the source region closer to a back surface of the semiconductor layer to be in contact with the source region, a first conductivity type drain region formed on a side of the channel region closer to the back surface of the semiconductor layer to be in contact with the channel region, a gate insulating film formed on an inner surface of the gate trench, and a gate electrode embedded inside the gate insulating film in the gate trench, while the channel region includes a channel portion formed along the side surface of the gate trench so that a channel is formed in operation and a projection projecting from an end portion of the channel portion closer to the back surface of the semiconductor layer toward the back surface.
US09502489B2
Provided is a semiconductor device having improved reliability. Over a semiconductor substrate, a first coil is formed via a first insulating film. A second insulating film is formed so as to cover the first insulating film and the first coil. Over the second insulating film, a pad is formed. Over the second insulating film, a multi-layer film having an opening exposing a part of the pad is formed. Over the multi-layer insulating film, a second coil is formed. The second coil is placed over the first coil. The second and first coils are magnetically coupled to each other. The multi-layer film includes a silicon dioxide film, a silicon nitride film over the silicon dioxide film, and a resin film over the silicon nitride film.
US09502486B2
An organic light-emitting diode (OLED) display having thin film transistors (TFTs) is disclosed. In one aspect, TFTs of the OLED display include a substrate and a first semiconductor layer formed over the substrate and including first channel, source, and drain regions and a lightly doped region between the first channel region and the first source and drain regions. The OLED display also includes a second semiconductor layer formed over the substrate and including second channel, source, and drain regions. The OLED display further includes first and second gate electrodes formed over the first semiconductor layer and a third gate electrode formed over the second semiconductor layer. The width of the second gate electrode is less than that of the first gate electrode and the lightly doped region overlaps a portion of the first gate electrode and does not overlap the second gate electrode.
US09502485B2
Organic light-emitting diode (OLED) displays and methods of manufacturing OLD displays are disclosed. In one aspect, an OLED display includes a substrate having an emission area and a non-emission area, a pixel electrode formed in the emission area, and an intermediate layer formed over the pixel electrode and including an organic emission layer. The display also includes an opposite electrode formed in the emission and non-emission areas and at least partially covering the intermediate layer. The display further includes a black matrix formed over the opposite electrode and including a first light-blocking portion formed in the non-emission area and a second light-blocking portion formed in the emission area and having light transmittance greater than that of the first light-blocking portion.
US09502477B2
A display apparatus and a filter for improving color purity (color saturation filter) are disclosed. In one aspect, the display apparatus includes a substrate, a display device formed on the substrate and having a plurality of pixel areas that emit different colors of light, and a color saturation filter on the display device. The color saturation filter is formed with a substantially uniform thickness over the plurality of pixel areas and has a transmissivity such that a full width at half maximum at the central wavelength of blue light emitted from one of the pixel areas is about 100 nm or less.
US09502475B2
Disclosed is an organic light emitting device. The organic light emitting device includes a first emission unit configured to include a first red emission layer which emits red light, a first green emission layer which emits green light, and a first blue emission layer which emits blue light, a second emission unit configured to include a second red emission layer which emits red light, a second green emission layer which emits green light, and a second blue emission layer which emits blue light, a charge generation layer disposed between the first emission unit and the second emission unit, a first electrode formed as a reflective electrode, and configured to supply an electric charge having a first polarity to the first emission unit and the second emission unit, and a second electrode configured to supply an electric charge having a second polarity to the first and second emission units.
US09502474B2
A method of fabricating an organic electroluminescent display includes: forming a plastic layer on a substrate including a first pixel region; patterning the first plastic layer to form a first opening in the first pixel region; forming a first organic light emitting layer on the first plastic layer having the first opening; and removing the first plastic layer from the substrate to form a first organic light emitting pattern in the first opening.
US09502473B2
An organic photoelectronic device includes a first electrode and a second electrode facing each other, and an active layer between the first electrode and the second electrode, the active layer including a first compound having a maximum absorption wavelength of about 500 nm to about 600 nm in a visible ray region and a transparent second compound in a visible ray region.
US09502464B2
A method of manufacturing an optical image stabilizer including providing a silicon-on-insulator (SOI) substrate that includes first and second silicon each provided on an upper surface and a lower surface of the substrate, having an insulator layer therebetween, forming a table, a cantilever arm connected to the table, an anchor connected to the cantilever arm, and an electrode opposite to the cantilever arm by etching the first silicon, allowing the table and the cantilever arm to levitate from the second silicon by removing an insulator layer disposed under the table and the cantilever arm, and mounting an image sensor on the table.
US09502462B1
An integrated circuit (IC) sensor is described. The IC sensor includes a pixel array and IC components. The pixel array has a plurality of pixels, wherein each pixel includes an EMR absorption region including a detector material having a plurality of nanoparticles embedded in a matrix material and exhibiting a nano-plasmonic property. The IC components are arranged to provide amplification of a voltage signal from the EMR absorption region, and to select the voltage signal from the EMR absorption region.
US09502452B2
Each of multiple pixels includes a photoelectric conversion unit. A first holding unit is configured to hold a charge generated by the photoelectric conversion unit, at a location different from location of the photoelectric conversion unit. A second holding unit is configured to hold a charge held by the first holding unit at a location different from locations of both of the first holding unit and the photoelectric conversion unit. An amplifying unit includes an input node different from the second holding unit and is configured to output a signal based on a charge transferred to the input node from the second holding unit. A first discharge unit includes a charge draining node which is electrically connected to a line where a predetermined voltage is supplied. The first discharge unit discharges a charge held by the first holding unit to the charge draining node.
US09502449B2
A semi-reflective display and a method for fabricating and assembling a semi-reflective display are presented, where the display may be comprised of visible light rectifying antenna arrays tuned to four different colors, which when forward biased may use electric power to amplify reflected colored light, and when reversed biased may generate electric power by absorbing light. TFT-tunnel diode logic may be used to control each sub-pixel.
US09502442B2
A thin film transistor array substrate and a method of manufacturing the thin film transistor array substrate are provided. The thin film transistor array substrate may include: a substrate; a thin film transistor (TFT) including an active layer, a gate electrode, a source electrode, and a drain electrode on the substrate. The gate electrode may include a bottom gate electrode and a top gate electrode that covers upper and lateral surfaces of the bottom gate electrode.
US09502439B2
An array substrate comprises a plurality of subpixels, each of the subpixels comprising: at least one thin film transistor, an organic resin layer, and uncontacted first pixel electrode and second pixel electrode arranged along the data line direction; the first pixel electrode extends to the above of a first gate line, the second pixel electrode extends to the above of a second gate line, the first gate line and the second gate line are adjacent to each other; the first pixel electrodes of two adjacent subpixels located at two sides of the first gate line are connected above the first gate line, the second pixel electrodes of two adjacent subpixels located at two sides of the second gate line are connected above the second gate line.
US09502438B2
An array substrate and manufacturing thereof are provided. The array substrate comprises gate lines, first data lines, second data lines and N×M pixel units defined by the gate lines intersecting with the first data lines and the second data lines. A repairing line for each column of the pixel units is provided for a region at which at least one row of pixel units are located. Projections of two ends of the repairing line on the substrate respectively overlap with regions at which the first data line and the second data line of the same column of pixel units are located, and the repairing line is isolated from the first data line and the second data line.
US09502431B2
According to one embodiment, a memory device includes a first stacked layer structure stacked in order of a first insulating layer, a first electrode layer, . . . an n-th insulating layer, an n-th electrode layer, and an (n+1)-th insulating layer in a first direction perpendicular to a surface of a semiconductor substrate, where n is a natural number, an oxide semiconductor layer extending through the first to n-th electrode layers in the first direction, a second stacked layer structure provided between the first to n-th electrode layers and the oxide semiconductor layer, and including a charge storage layer which storages charges, and a area provided in the oxide semiconductor layer.
US09502420B1
A method is provided that includes providing a material stack of, from bottom to top, a relaxed and n-type doped silicon germanium alloy layer and a relaxed silicon germanium alloy layer, each layer having a uniform germanium content, on a surface of a relaxed and graded silicon germanium alloy buffer layer that is located within a pFET device region of a semiconductor substrate. Next, the relaxed silicon germanium alloy layer is patterned to provide at least one relaxed silicon germanium alloy fin having the uniform germanium content on the relaxed and n-type doped silicon germanium alloy layer. A strained germanium layer is then formed surrounding the at least one relaxed silicon germanium alloy fin. A portion of the strained germanium layer and the at least one relaxed silicon germanium alloy fin can be used as composited channel material for fabricating a pFinFET device.
US09502419B2
A FinFET device comprises a well over a substrate, an isolation region over the well and a fin line over the well and surrounded by the isolation region, wherein the fin line is wrapped by a first gate electrode structure to form a first transistor and an end of the fin line is of a tapered shape.
US09502417B2
A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.
US09502416B1
A semiconductor device includes first through fourth areas, first through fourth gate stacks, the first gate stack includes a first high-dielectric layer, a first TiN layer to contact the first high-dielectric layer, and a first gate metal on the first TiN layer, the second gate stack includes a second high-dielectric layer, a second TiN layer to contact the second high-dielectric layer, and a second gate metal on the second TiN layer, the third gate stack includes a third high-dielectric layer, a third TiN layer to contact the third high-dielectric layer, and a third gate metal on the third TiN layer, and the fourth gate stack includes a fourth high-dielectric layer, a fourth TiN layer to contact the fourth high-dielectric layer, and a fourth gate metal on the fourth TiN layer, the first through fourth thicknesses of the TiN layers being different.
US09502415B2
The disclosed technology generally relates to complementary metal-oxide-silicon (CMOS) devices, and more particularly to an n-channel metal-oxide-silicon (nMOS) device and a p-channel metal-oxide-silicon (pMOS) device that are under different types of strains. In one aspect, a method comprises providing trenches in a dielectric layer on a semiconductor substrate, where at least a first trench defines an nMOS region and a second trench defines a pMOS region, and where the trenches extend through the dielectric layer and abut a surface of the substrate. The method additionally includes growing a first seed layer in the first trench on the surface and growing a common strain-relaxed buffer layer in the first trench and the second trench, where the common strain-relaxed buffer layer comprises silicon germanium (SiGe). The method further includes growing a common channel layer comprising germanium (Ge) in the first and second trenches and on the common strain-relaxed buffer layer. The properties of the first seed layer and the common strained relaxed buffer layer are predetermined such that the common channel layer is under a tensile strain or is unstrained in the nMOS region and is under a compressive strain in the pMOS region. Aspects also include devices formed using the method.
US09502414B2
An integrated circuit (IC) device may include a first active transistor of a first-type in a first-type region. The first active transistor may have a first-type work function material and a low channel dopant concentration in an active portion of the first active transistor. The IC device may also include a first isolation transistor of the first-type in the first-type region. The second active transistor may have a second-type work function material and the low channel dopant concentration in an active portion of the first isolation transistor. The first isolation transistor may be arranged adjacent to the first active transistor.
US09502411B1
A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.
US09502405B1
A plurality of contact trenches are formed in a semiconductor structure. The plurality of contact trenches are formed with a contact opening width selected to result in improper contact trench formation in a random number of the plurality of contact trenches. Devices are formed from the semiconductor structure using the plurality of contact trenches, wherein devices formed with improperly formed contact trenches are defective and devices formed with properly formed contact trenches are not defective. One or more measurements are performed to determine which devices are defective and which devices are not defective. The results of the measuring step represent a unique authentication code for an integrated circuit in which the devices are formed. Advantageously, the unique authentication code represents a physically unclonable function.
US09502403B2
A method for fabricating a semiconductor device includes providing a semiconductor substrate, forming on the semiconductor substrate a dummy gate interface layer and a dummy gate of a core device and a gate interface layer and a dummy gate of an IO device, removing the dummy gates of the core and IO devices, removing the dummy gate interface layer of the core device, forming a gate interface layer in the original location of the removed dummy gate interface layer, forming a high-k dielectric layer each on the gate interface layer of the core and IO devices, and submitting the semiconductor substrate to a high-pressure fluorine annealing. The high-pressure fluorine annealing causes the gate interface layer and the high-k dielectric layer of the core and IO devices to be doped with fluoride ions.
US09502402B2
A semiconductor device includes: a semiconductor layer having a first end portion and a second end portion; a first main electrode provided on the first end portion and electrically connected to the semiconductor layer; a second main electrode provided on the second end portion and electrically connected to the semiconductor layer; a first gate electrode provided via a first gate insulating film in a plurality of first trenches formed from the first end portion toward the second end portion; and a second gate electrode provided via a second gate insulating film in a plurality of second trenches formed from the second end portion toward the first end portion. Spacing between a plurality of the first gate electrodes and spacing between a plurality of the second gate electrodes are 200 nm or less.
US09502397B1
A method of making a semiconductor component package can include providing a substrate comprising conductive traces, soldering a surface mount device (SMD) to the substrate with solder, encapsulating the SMD on the substrate with a first mold compound over and around the SMD to form a component assembly, and mounting the component assembly to a temporary carrier with a first side of the component assembly oriented towards the temporary carrier. The method can further include mounting a semiconductor die comprising a conductive interconnect to the temporary carrier adjacent the component assembly, encapsulating the component assembly and the semiconductor die with a second mold compound to form a reconstituted panel, and exposing the conductive interconnect and the conductive traces at the first side and the second side of the component assembly with respect to the second mold compound.
US09502395B2
In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier.
US09502394B2
Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.
US09502393B2
Disclosed is a display device including features that suppresses threshold voltage variation among the oxide thin-film transistors of an array substrate and a method for manufacturing the same. The display device includes a first COG block including sub-pixels configured to receive an output signal from a first drive integrated circuit positioned in a first COG area; a second COG block including sub-pixels configured to receive an output signal from a second drive integrated circuit positioned in a second COG area; and an equipotential line extended from the first COG area to the second COG area.
US09502390B2
A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed contacting an edge surface of the wire bonds which separates adjacent wire bonds from one another. Further processing comprises removing at least portions of the first element, wherein the interposer has first and second opposite sides separated from one another by at least the encapsulation, and the interposer having first contacts and second contacts at the first and second opposite sides, respectively, for electrical connection with first and second components, respectively, the first contacts being electrically connected with the second contacts through the wire bonds.
US09502385B2
A package-on-package (POP), including a semiconductor device, and a multi-chip-package located above the semiconductor device, wherein the semiconductor device includes a substrate including a first surface, a plurality of electrodes formed on the first surface, a second surface opposite to the first surface, a plurality of lands formed on the second surface, and a plurality of wirings, (a2) a semiconductor chip mounted over the first surface of the substrate, and (a3) a plurality of first solder balls formed on the lands, respectively, wherein the multi-chip-package is electrically connected with the semiconductor device via a plurality of second solder balls, wherein the plurality of second solder balls are connected with the plurality of electrodes, respectively.
US09502378B1
A method of manufacturing a semiconductor package is provided. The method includes providing a strip substrate having a plurality of unit substrate regions that are spaced apart from each other by a periphery region and have blind vias, a peripheral conductive pattern layer disposed in the periphery region, and a connection pattern layer electrically connecting the blind vias to the peripheral conductive pattern layer. Semiconductor chips are disposed on the plurality of unit substrate regions, respectively. Conductive wires are formed to electrically connect connection pads disposed on the plurality of unit substrate regions to bonding pads disposed on the semiconductor chips. The connection pads are electrically connected to the blind vias, and forming the conductive wires includes performing a test for confirming a current that flows between each conductive wire and the peripheral conductive pattern layer through the unit substrate region.
US09502372B1
An apparatus relates generally to a microelectronic package. In such an apparatus, a microelectronic die has a first surface, a second surface opposite the first surface, and a sidewall surface between the first and second surfaces. A plurality of wire bond wires with proximal ends thereof are coupled to either the first surface or the second surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from either the first surface or the second surface, respectively, of the microelectronic die. A portion of the plurality of wire bond wires extends outside a perimeter of the microelectronic die into a fan-out (“FO”) region. A molding material covers the first surface, the sidewall surface, and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to an outer surface of the molding material.
US09502368B2
A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An embodiment for fabricating such a microelectronic package may include forming a microelectronic die having an active surface and an opposing back surface, wherein the microelectronic die active surface may be attached to a microelectronic substrate. A picture frame stiffener having an opening therethrough may be formed and placed on a release film, wherein a mold material may be deposited over the picture frame stiffener and the release film. The microelectronic die may be inserted into the mold material, wherein at least a portion of the microelectronic die extends into the picture frame opening. The release film may be removed and a portion of the mold material extending over the microelectronic die back surface may then be removed to form the microelectronic package.
US09502360B2
A stress compensation for use in packaging, and a method of forming, is provided. The stress compensation layer is placed on an opposing side of a substrate from an integrated circuit die. The stress compensation layer is designed to counteract at least some of the stress exerted structures on the die side of the substrate, such as stresses exerted by a molding compound that at least partially encapsulates the first integrated circuit die. A package may also be electrically coupled to the substrate.
US09502355B2
A system, method, and computer program product are provided for producing a high bandwidth bottom package of a die-on-package structure. The method includes the steps of receiving a bottom package comprising a substrate material having a top layer and an integrated circuit die that is coupled to the top layer of the substrate material. A first set of pads is formed on the top layer of the substrate material and a layer of dielectric material is applied on a top surface of the bottom package to cover the integrated circuit die and the first set of pads.
US09502354B2
A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern.
US09502353B2
The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
US09502350B1
Methods of forming an interconnect structure include depositing a first conductive material on a substrate. Aspects include subtractively etching the conductive material to form a patterned first conductive layer, and depositing a dielectric layer on interconnect structure. Aspects also include depositing a second conductive material on the dielectric layer and removing the second conductive material through the top of the second metal liner.
US09502343B1
A structure includes a metal pad, a passivation layer having a portion covering edge portions of the metal pad, and a dummy metal plate over the passivation layer. The dummy metal plate has a plurality of through-openings therein. The dummy metal plate has a zigzagged edge. A dielectric layer has a first portion overlying the dummy metal plate, second portions filling the first plurality of through-openings, and a third portion contacting the first zigzagged edge.
US09502341B2
Embodiments of the inventive aspect include a printed circuit board and a semiconductor package using the same. The semiconductor package includes a substrate having one or more connection pads, semiconductor chips mounted on the substrate, an underfill layer filling a region between the semiconductor chips and the substrate, and solder bumps electrically connecting the connection pads and the semiconductor chips in the underfill layer. The substrate includes void preventing patterns protruding on a top surface of the substrate under the underfill layer.
US09502340B2
A method for manufacturing a wiring board according to the present invention includes the steps of preparing a supporting substrate having a product forming region and a marginal region; preparing a separable metal foil whose area is larger than that of the product forming region and is smaller than that of the supporting substrate; fixing the separable metal foil to the supporting substrate by burying into the supporting substrate; forming a build-up section on the buried separable metal foil; integrally cutting out the supporting substrate, the separable metal foil and the build-up section; obtaining a laminated body for wiring board composed of the second metal foil and the build-up section by separating the first metal foil and the second metal foil; and forming the wiring conductor layer by removing a part of the second metal foil.
US09502339B2
A resin-encapsulated semiconductor device having a semiconductor chip which is prevented from being damaged. The resin-encapsulated semiconductor device (100) comprises a semiconductor chip (1) including a silicon substrate, a die pad (10) to which the semiconductor chip (1) is secured through a first solder layer (2), a resin-encapsulating layer (30) encapsulating the semiconductor chip (1), and lead terminals (21) electrically connected to the semiconductor chip (1) and including inner lead portion (21b) covered with the resin-encapsulating layer (30). The lead terminals (21) are made of copper or a copper alloy. The die pad (10) is made of 42 alloy or a cover alloy and has a thickness (about 0.125 mm) less than the thickness (about 0.15 mm) of the lead terminals (21).
US09502338B2
In one implementation, a semiconductor package includes a patterned conductive carrier including partially etched segments. The semiconductor package also includes a control FET having a control drain attached to a first partially etched segment of the patterned conductive carrier. In addition, the semiconductor package includes a sync FET having a sync source and a sync gate attached to respective second and third partially etched segments of the patterned conductive carrier. The semiconductor package further includes a heat spreading conductive plate situated over a control source of the control FET and over a sync drain of the sync FET so as to couple the control source and the sync drain to a switch node segment of the patterned conductive carrier.
US09502337B2
Flip-chip on leadframe (FCOL) semiconductor packaging structure and fabrication method thereof are provided. A semiconductor chip with copper pillars formed there-over is provided. A barrier layer is formed on the copper pillars. A solder material is coated on the barrier layer. A layer of soldering flux is coated on the solder material. A leadframe with electric leads formed thereon is provided. An insulating layer is formed an the leadframe and having a plurality of openings to expose portion of the electric leads. The semiconductor chip is placed upside down onto the leadframe to have the soldering flux in contact with the portion of the electric leads exposed in the openings. The solder material flows back to form conductive interconnections between the copper pillars and the portion of the electric leads exposed in the openings. The semiconductor chip is packaged with the leadframe using a mold compound.
US09502329B2
A semiconductor module cooler supplies a cooling medium to a cooling medium jacket from outside to cool a plurality of semiconductor elements thermally connected to the cooling medium jacket through a heat sink. The cooling medium jacket has a cooling fin cooling room including an opening for inserting cooling fins, and cooling the cooling fins; a cooling medium introduction port to introduce the cooling medium; a cooling medium diffusion room to diffuse and supply the cooling medium to the cooling fin cooling room; a cooling medium diffusion wall provided in the cooling medium diffusion room in which the cooling medium diffused by the cooling medium diffusion room flows over to be introduced to the cooling fin cooling room side; a cooling medium discharge port discharging the cooling medium to the outside; and a cooling medium convergence room provided between the cooling fin cooling room and the cooling medium discharge port.
US09502326B2
A semiconductor device includes a transistor, a package in which the transistor is molded, a first heatsink plate, and a second heatsink plate. The first heatsink plate is bonded to a first surface of the package, and is fixed to one surface of the transistor in the package. The second heatsink plate is bonded to a second surface of the package so as to be opposed to the first heatsink plate, and is fixed to the transistor in the package. The second surface is opposite to the first surface. A bonded surface of the first heatsink plate with the plastic body includes a high stress area in which tensile stress equal to or higher than a predetermined stress value is generated. A plurality of grooves are provided in the high stress area.
US09502322B2
One of the embodiments for a package substrate discloses a molding compound having plurality of metal pillar with middle portion embedded therein; a top end of the metal pillar protrudes above the molding compound; a bottom end of the metal pillar protrudes below the molding compound; a bottom RDL is configured on bottom of the molding compound; the RDL has a plurality of top metal pad and a plurality of bottom metal pad; a density of the plurality of bottom metal pad is higher than the density of the plurality of top metal pad; each metal pillar metal pad is electrically coupled to a corresponding first top metal pad.
US09502315B2
A stacked semiconductor arrangement is provided. The stacked semiconductor arrangement includes a dynamic pattern generator layer having an electrical component. The arrangement also includes a monitoring layer configured to evaluate electrical performance of the electrical component.
US09502309B1
A method of making a semiconductor device includes forming a first trench contact over a first source/drain region of a first transistor; forming a second trench contact over a second source/drain region of a second transistor; depositing a first liner material within the first trench contact; and depositing a second liner material within the second trench contact; wherein the first liner material and the second liner material include different materials.
US09502307B1
An approach to forming a semiconductor structure with improved negative bias temperature instability includes forming an interfacial layer on a semiconductor substrate with an nFET and a pFET. The approach includes depositing a gate dielectric layer on the interfacial layer. Additionally, the approach includes an nFET work function metal layer deposited on the interfacial layer. Additionally, the approach includes removing the nFET work function metal from an area above the pFET and depositing a pFET work function metal layer on a portion of the exposed gate dielectric layer where the portion of the exposed gate dielectric layer is over the pFET. Furthermore, the approach includes depositing a gate metal on the pFET work function metal layer where the gate metal is deposited in an environment with a fluorine containing gas followed by an anneal in a reducing environment.
US09502305B2
A CMOS transistor and a method for manufacturing the same are disclosed. A semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided. The source/drain of the PMOS transistor comprises SiGe epitaxial layer. A carbon implantation process is performed to form a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. A silicide layer is formed on the source/drain. A CESL is formed on the PMOS transistor and the NMOS transistor. The formation of the carbon-doped layer is capable of preventing Ge out-diffusion.
US09502304B2
Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a drain region of the second conductivity type, and the diode circuit is connected between the isolation structure and the drain region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s).
US09502299B2
A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
US09502296B2
In an exemplary implementation, a method includes growing a III-Nitride body over a group IV substrate in a semiconductor wafer. The method includes forming at least one device layer over the III-Nitride body. The method also includes etching grid array trenches in the III-Nitride body, where the etching of the grid array trenches may extend into the group IV substrate. The method can also include forming an edge trench around a perimeter of the semiconductor wafer. The method further includes forming separate dies by cutting the semiconductor wafer approximately along the grid array trenches.
US09502291B2
A semiconductor memory device includes a first insulating layer covering a substrate, a first contact plug and a second contact plug each penetrating the first insulating layer, a first data storage element disposed on the first contact plug, and a second data storage element disposed on the second contact plug. The first contact plug includes a vertically extending portion and a horizontally extending portion arranged between the vertically extending portion and the first data storage element, and the second contact plug extends substantially vertically from a top surface of the substrate. The first data storage element is laterally spaced apart from the vertically extending portion when viewed in plan view. The first data storage element is disposed on the horizontally extending portion.
US09502287B2
A device includes a substrate and at least three conducting features embedded into the substrate. Each conducting feature includes a top width x and a bottom width y, such that a top and bottom width (x1, y1) of a first conducting feature has a dimension of (x1
US09502282B2
In a method of manufacturing a semiconductor device using high-NA ArF liquid immersion exposure of a photoresist, a layer arrangement is provided capable of increasing reflection of a reference beam in an oblique incidence autofocus optical system, thereby enhancing autofocus and making it possible to reduce variation in the diameter of a contact hole.
US09502279B2
An apparatus and method adapted to mount an elastomer band in a mounting groove around a semiconductor substrate support used for supporting a semiconductor substrate in a plasma processing chamber, which includes an installation unit having a top ring, a clamp ring, and a base ring, and upon tightening of the top ring onto the base ring, the elastomer band is clamped between the clamp ring and the base ring, and a clamping surface adapted to release the elastomer band on at least one of a lower surface of the clamp ring and/or an upper surface of the base ring. A latch and release mechanism, which releases the elastomer band into the mounting groove by declamping the elastomer band from between the clamp ring and the base ring.
US09502277B2
An apparatus, in particular end effector, for receiving, transporting and/or positioning a wafer frame which is covered by a carrier film for carrying a wafer, has a holder which has vacuum nozzles for holding the wafer frame on the apparatus, and has a centering device which has at least one stop, which can engage in a cutout in the wafer frame, for centering the wafer frame. In order to precisely position the wafer frame, the holder has Bernoulli nozzles for holding and moving the wafer frame in the direction of the stop without contact, and the stop is mounted such that it can be adjusted against the movement direction generated by the Bernoulli nozzles from an initial position to a centering position, which differs from the initial position, for centering the wafer frame.
US09502273B2
A heat treatment apparatus includes a chamber for receiving a substrate therein, and a measurement part for measuring an air particle concentration in a processing space provided in the chamber. An air particle concentration in the processing space provided in the chamber is measured by the measurement part. The air particle concentration is correlated with the number of particles attached to a substrate received in the chamber. Accordingly, by conducting a particle test after the air particle concentration in the processing space is lowered to an air particle concentration corresponding to the number of particles existing on the substrate which can pass the particle test, the number of times the particle test should be conducted after maintenance of the heat treatment apparatus can be reduced.
US09502272B2
Devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a device includes a first semiconductor device and a second semiconductor device coupled to the first semiconductor device. An underfill material is disposed between the first semiconductor device and the second semiconductor device. The underfill material is also disposed on sidewalls of the first semiconductor device and the second semiconductor device. The underfill material has a first thickness on sidewalls of the first semiconductor device and a second thickness on sidewalls of the second semiconductor device. The second thickness is different than the first thickness.
US09502271B2
Flexible structures and method of providing a flexible structure are disclosed. In some embodiments, a method of providing a flexible structure includes: providing a flex substrate having a device bonded to a first side of the flex substrate; and attaching a rigid layer to a second side of the flex substrate opposite the first side using an adhesive layer.
US09502270B2
Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature.
US09502263B2
Implementations described herein generally relate to methods for depositing etch stop layers, such as AlN layers, using UV assisted CVD. Methods disclosed herein generally include positioning a substrate in a process region of a process chamber; delivering an aluminum-containing precursor to the process region, the aluminum-containing precursor depositing an aluminum species onto the substrate; purging the process region of aluminum-containing precursor using an inert gas; delivering a UV responsive nitrogen-containing precursor to the process region, the UV responsive nitrogen-containing gas being activated using UV radiation to create nitrogen radicals, the nitrogen radicals reacting with the aluminum species to form an AlN layer; and purging the process region of UV responsive nitrogen-containing precursor using an inert gas.
US09502258B2
A method of anisotropically dry-etching exposed substrate material on a patterned substrate is described. The patterned substrate has a gap formed in a single material made from, for example, a silicon-containing material or a metal-containing material. The method includes directionally ion-implanting the patterned structure to implant the bottom of the gap without implanting substantially the walls of the gap. Subsequently, a remote plasma is formed using a fluorine-containing precursor to etch the patterned substrate such that either (1) the walls are selectively etched relative to the floor of the gap, or (2) the floor is selectively etched relative to the walls of the gap. Without ion implantation, the etch operation would be isotropic owing to the remote nature of the plasma excitation during the etch process.
US09502246B2
A method of forming an oxide semiconductor device may be provided. In the method, a substrate comprising a first major surface and a second major surface that faces away from the first major surface may be provided. An oxide semiconductor device may be formed over the first major surface to provide an intermediate device, and the semiconductor device may comprise an oxide active layer. The intermediate device may be subjected to ultraviolet (UV) light (e.g., ultraviolet ray irradiation process) for a first period, and subjected to heat (e.g., thermal treatment process) for a second period. The first and second periods may at least partly overlap.
US09502237B2
Provided are a substrate processing apparatus, a method of manufacturing a semiconductor device and a non-transitory computer-readable recording medium. The substrate processing apparatus includes a process chamber configured to process a substrate; a gas supply unit including gas supply holes configured to independently supply a process gas for processing the substrate to each of a central portion of the substrate and a peripheral portion of the substrate in the process chamber; an exhaust unit configured to exhaust an inside of the process chamber; and a control unit configured to control the gas supply unit to supply the process gas to the central portion of the substrate after the process gas is supplied to the peripheral portion of the substrate through the gas supply unit.
US09502234B2
Described herein are methods of forming dielectric films such as non-porous dielectric films, comprising silicon, oxide, and optionally nitrogen, carbon, hydrogen, and boron. Also disclosed herein are the methods to form dielectric films or coatings on an object to be processed, such as, for example, a semiconductor wafer. Specifically the methods include silanes that have bulky alkoxy groups as well as SiH groups. Examples of such silanes used in the methods including di-tert-pentoxysilane, di-tert-butoxysilane and silanes having the formula (H)2Si(OR)(OR1) wherein R is tert-butyl and R1 is selected from the group consisting of methyl, propyl, isopropyl, butyl, isobutyl, sec-butyl, pentyl, isopentyl, tert-pentyl and hexyl.
US09502210B2
An ion implanter includes: a beam deflector that deflects an ion beam passing through a previous stage beam path and outputs the beam to pass through a subsequent stage beam path toward a wafer; a beam filter slit that partially shields the beam traveling through the subsequent stage beam path and allows passage of a beam component having a predetermined trajectory toward the wafer; a dose cup that is disposed between the beam deflector and the beam filter slit and measures a part of the beam exiting from the beam deflector as a beam current; and a trajectory limiting mechanism that is disposed between the beam deflector and the dose cup and prevents a beam component having a trajectory deviated from the predetermined trajectory from being incident to a measurement region of the dose cup.
US09502209B2
Disclosed are an apparatus, system, and method for scanning a substrate or other workpiece through a gas-cluster ion beam (GCIB), or any other type of ion beam. The workpiece scanning apparatus is configured to receive and hold a substrate for irradiation by the GCIB and to scan it through the GCIB in two directions using two movements: a reciprocating fast-scan movement, and a slow-scan movement. The slow-scan movement is actuated using a servo motor and a belt drive system, the belt drive system being configured to reduce the failure rate of the workpiece scanning apparatus.
US09502208B2
A stage system includes a stage that holds an object, a linear motor mechanism that moves the stage by a thrust force generated by a current flowing through the coil, and a control section that controls the current flowing through the coil. The current flowing through the coil in a state where the stage is maintained in the static state be greater than a minimum current amount required for generating the thrust force greater than a maximum static friction force of the stage with respect to the guide rails.
US09502180B2
A multilayer ceramic capacitor may include: a ceramic body; first and second external electrodes; first and second internal electrodes connected to the first and second external electrodes, respectively; first floating electrodes having both end portions overlapped with portions of the first and second internal electrodes, respectively; and at least one second floating electrode shifted with respect to the first floating electrodes in a length direction of the ceramic body. The lengths of portions of the first and second floating electrodes overlapped with the portions of the first internal electrodes may be different from those of portions of the first and second floating electrodes overlapped with the portions of the second internal electrodes.
US09502179B2
A metallized film composed of a dielectric film, a metal thin film layer and a dielectric layer, the metal thin film layer being formed on at least one surface of the dielectric film, the dielectric layer being formed on the metal thin film layer, and the dielectric layer being composed of acrylic acid ester resin as a main component being composed of dimethylol tricyclodecane diacrylate and monoacrylate containing a heterocycle.
US09502178B2
A monolithic capacitor includes a laminated body including stacked dielectric layers and substantially in the shape of a rectangular parallelepiped, and including a first surface being a mounting surface, a second surface opposite to the first surface, opposing third and fourth surfaces orthogonal to the first and second surfaces, and opposing fifth and sixth surfaces orthogonal to the first to fourth surfaces; capacitor electrodes disposed in the laminated body and each including a capacitive portion and a lead portion extending therefrom to at least one surface of the laminated body, the capacitive portions facing each other with dielectric layers interposed therebetween; and first and second outer electrodes disposed on at least one surface of the laminated body and connected to the lead portions. A gap between the first surface and the capacitive portions is greater than a gap between the second surface and the capacitive portions.
US09502177B2
A multilayer ceramic capacitor may include: a ceramic body including dielectric layers and having first and second main surfaces opposing each other, first and second side surfaces opposing each other, and first and second end surfaces opposing each other; an active layer configured to form capacitance by including first and second internal electrodes disposed to face each other with the dielectric layer interposed therebetween and alternately exposed to the first or second side surface; and a first external electrode disposed on the first side surface and electrically connected to the first internal electrodes and a second external electrode disposed on the second side surface and electrically connected to the second internal electrodes. When length of the ceramic body is L and length of the first and second external electrodes in the length direction of the ceramic body is L1, 0.2≦L1/L≦0.96 is satisfied.
US09502168B1
In one embodiment, an integrated circuit is described. The integrated circuit includes a substrate, a dielectric stack, a first inductor and a second inductor. The dielectric stack may be formed above the substrate and includes first and second layers. The first inductor may be formed in both the first and second layers. The second inductor may also be formed in the first and second layers with a substantial portion of the first inductor structure overlaps with the second inductor structure.
US09502162B2
A PTC circuit protection device includes a PTC polymer material and two electrodes attached to the PTC polymer material. The PTC polymer material includes a polymer matrix and a particulate conductive filler dispersed in the polymer matrix, the conductive filler including conductive non-carbonaceous particles and conductive carbon particles. The conductive carbon particles have an average particle size ranging from 40 to 100 nm, a DBP oil-absorption ranging from 60 to 120 cc/100 g, and a volatile content ranging from 0.2 to 2.0 wt %. The conductive carbon particles are in an amount ranging from 1 to 14 wt % based on the total weight of the PTC polymer material.
US09502159B2
A superconducting wire connection structure comprises a first superconducting wire and a second superconducting wire, ends of which are arranged across from each other, and a third superconducting wire which spans and connects the first superconducting wire and the second superconducting wire along a longitudinal direction of the first superconducting wire and the second superconducting wire. Each of the first superconducting wire, the second superconducting wire and the third superconducting wire is a tape-shaped superconducting wire which includes a substrate laminated with at least a superconductive layer. The third wire is narrower in at least one portion than the first superconducting wire and the second superconducting wire.
US09502152B2
According to example embodiments, a method includes dispersing carbon nanotubes in a mixed solution containing a solvent, the carbon nanotubes, and a dispersant, the carbon nanotubes including semiconducting carbon nanotubes, the dispersant comprising a polythiophene derivative including a thiophene ring and a hydrocarbon sidechain linked to the thiophene ring. The hydrocarbon sidechain includes an alkyl group containing a carbon number of 7 or greater. The hydrocarbon sidechain may be regioregularly arranged, and the semiconducting carbon nanotubes are selectively separated from the mixed solution. An electronic device includes semiconducting carbon nanotubes and the foregoing described polythiophene derivative.
US09502150B2
The invention relates generally to field grading materials and, more particularly, to field grading materials including graphene oxide, reduced graphene oxide, or both, exhibiting non-linear resistivity. In one embodiment, the invention provides a composite material comprising: a polymer material; and reduced graphene oxide distributed within the polymer material.
US09502149B2
A UV system for irradiating a substrate includes a lamphead having an enclosure with an interior. A UV bulb is positioned in the interior and is capable of emitting UV energy when excited by RF energy. The UV system also includes a solid state RF source capable of generating the RF energy. The RF energy is transmitted to the UV bulb, which causes the UV bulb to ignite and emit the UV energy from the interior of the lamphead.
US09502145B2
Illustrative embodiments provide for the operation and simulation of the operation of fission reactors. Illustrative embodiments and aspects include, without limitation, nuclear fission reactors and reactor modules, including modular nuclear fission reactors and reactor modules, nuclear fission deflagration wave reactors and reactor modules, modular nuclear fission deflagration wave reactors and modules, methods of operating nuclear reactors and modules including the aforementioned, methods of simulating operating nuclear reactors and modules including the aforementioned, and the like.
US09502144B2
A wet filter for a nuclear reactor primary containment vent that employs an inclined manifold having a plurality of outlets that communicate through a first set of metal fiber filters submerged in a pool of water enclosed within a pressure vessel. A demister suspended above the pool of water to remove any entrained moisture in the filtered effluent before being passed through a second stage of higher density, dry, metal fiber filters connected to a second manifold that communicates with an outlet on the pressure vessel that is connected to an exhaust passage to the atmosphere.
US09502140B2
According to one embodiment, a semiconductor memory device includes first word lines connected to a memory cell array, second word lines connected to a redundancy area, a first row decoder configured to perform selecting from the first word lines based on a row address, a judgment circuit configured to determine whether or not a replacement operation with the redundancy area is needed based on a redundancy address included in the row address, and a second row decoder configured to perform selecting from the second word lines. The row address includes a first row address and a second row address input in order in a time-sharing method. The first row address includes all of the redundancy address.
US09502138B2
A method for encoding an input data block for storage in q-level cells of solid-state memory includes producing a preliminary block from the input data block by modulation encoding at least part of the input block into a first group of qary symbols via a first drift-tolerant encoding scheme, the preliminary block comprising the first group of qary symbols and any remainder of the input block not encoded via the first encoding scheme; generating parity data for the preliminary block via an error-correction encoding scheme; modulation encoding the parity data and any remainder of the input block into a second group of qary symbols via a second drift-tolerant encoding scheme; and supplying the qary symbols of the first and second groups for storage in respective q-level memory cells.
US09502137B2
In a method of optimizing a log likelihood ratio (LLR) used to correct errors related to data stored in a nonvolatile memory device, variation of threshold voltage distribution for a plurality of memory cells included in the nonvolatile memory device is monitored, and the LLR for the memory cells is updated based on a monitoring result. Although the characteristics of the memory cells are deteriorated, the LLR is continuously maintained to the optimal value.
US09502133B2
A memory cell (101) includes a memory transistor (10A) having channel length L1 and channel width W1, and a plurality of select transistors (10B) each electrically being connected in series with the memory transistor and independently having channel length L2 and channel width W2, wherein each of the memory transistor and the plurality of select transistors includes an active layer (7A) formed from a common oxide semiconductor film, the memory transistor is a transistor which is capable of being irreversibly changed from a semiconductor state where drain current Ids depends on gate voltage Vg to a resistor state where drain current Ids does not depend on gate voltage Vg, and channel length L2 is greater than channel length L1.
US09502130B2
According to one embodiment, a device includes a memory cell array including memory cells and controller. The controller executes verification of second data in a first verify period in a first verify operation and verification of third data in a second verify period in the first verify operation. The controller excludes memory cells to be written first data from a target of the first verify operation at a first time in the first verify period and excludes memory cells to be written the second data from the target at a second time in the second verify period.
US09502128B2
A method of operating a storage device may include receiving a read command and a read address, performing a read operation on selected memory cells corresponding to a selected string selection line and a selected word line based on the read address and performing a reliability verification read on unselected memory cells. Data read by the read operation may be output to an external device, and data read by the reliability verification read may be not output to the external device.
US09502125B2
In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The second memory plane is different than the first memory plane, but is in the same memory array as the first memory plane. The second page of memory cells has a different page address than the first page of memory cells.
US09502121B2
Memory cells of a nonvolatile memory array are characterized by one of multiple threshold voltage ranges including at least an erased threshold voltage range and a programmed threshold voltage range. Responsive to an erase command to erase a group of memory cells of the nonvolatile memory array, a plurality of phases are performed, including at least a pre-program phase and an erase phase. The pre-program phase programs a first set of memory cells in the group having threshold voltages within the erased threshold voltage range, and does not program a second set of memory cells in the group having threshold voltages within the erased threshold voltage range in the group. By not programming the second set of memory cells, the pre-program phase is performed more quickly than if the second set of memory cells were programmed along with the first set of memory cells.
US09502113B2
A Configurable Non-Volatile Content Addressable Memory (CNVCAM) cell consisting of a pair of complementary non-volatile memory devices and a MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor) is disclosed. The CNVCAM cells can be constructed to form the NOR-type match line memory array and the NAND-type match line memory array. In contrast to the Random Access Memory (RAM) accessed by the address codes with the prior knowledge of memory locations, CNVCAM can be pre-configured into non-volatile memory content data and searched by an input content data to trigger the further computing process. The unique property of CNVCAM can provide a key component for neural computing.
US09502098B2
A method of operating a first voltage regulator includes electrically coupling a transistor of an output stage of the first voltage regulator between a first power voltage and a second power voltage, and reverse biasing a bulk of the transistor by a back-bias circuit during a standby mode of a memory array. The first voltage regulator is coupled to a second voltage regulator and reverse biasing the bulk of the transistor reduces a contention current between the first voltage regulator and the second voltage regulator.
US09502095B1
A memory system is disclosed, which relates to a technology for reducing current consumption needed to perform a refresh operation in a Dual In-line Memory Module. The memory system includes a memory module, which includes a volatile memory and a non-volatile memory, and a host configured to provide a refresh command to the memory module during the refresh operation. The memory module is configured to store cell characteristic information of the volatile memory in the non-volatile memory in an idle state, and control a refresh operation of the volatile memory in response to the cell characteristic information.
US09502094B2
To provide a memory element which keeps a stored logic state even without supply of power. To increase an effect of reducing power consumption by facilitating stop of supply of power to the memory element for a short time. Data (potential) held in a node in a logic circuit can be swiftly saved on a node where one of a source and a drain of the transistor and one electrode of the capacitor included in a memory circuit are connected by lowering a potential of the other electrode of a capacitor before a transistor is turned on. By making a potential of the other electrode of the capacitor when the transistor is in an off state higher than a potential of the other electrode of the capacitor when the transistor is in an on state, a potential of the node can be reliably held even without supply of power.
US09502087B2
3-terminal magnetic circuits and devices based on the spin-transfer torque (STT) effect via a combination of injection of spin-polarized electrons or charged particles by using a charge current in a spin Hall effect metal layer coupled to a free magnetic layer and application of a gate voltage to the free magnetic layer to manipulate the magnetization of the free magnetic layer for various applications, including non-volatile memory functions, logic functions and others. The charge current is applied to the spin Hall effect metal layer via first and second electrical terminals and the gate voltage is applied between a third electrical terminal and either of the first and second electrical terminals. The spin Hall effect metal layer can be adjacent to the free magnetic layer or in direct contact with the free magnetic layer to allow a spin-polarized current generated via a spin Hall effect under the charge current to enter the free magnetic layer. The disclosed 3-terminal magnetic circuits can also be applied to signal oscillator circuits and other applications.
US09502085B2
A memory module comprises a module interface having module data-group ports to communicate data as respective data groups, a command port to receive memory-access commands, a first memory device including a first device data-group port, a second memory device including a second device data-group port, and a signal buffer coupled between the module interface and each of the first and second devices. In a first mode, in response to the memory-access commands, the signal buffer communicates the data group associated with each of the first and second device data-group ports via a respective one of the module data-group ports. In a second mode, in response to the memory-access commands, the signal buffer alternatively communicates the data group associated with the first device data-group port or the data group associated with the second device data-group port via the same one of the module data-group ports.
US09502083B2
A device includes a cutting circuit that is coupled between power supply lines in series with first and second output circuits which drive an output terminal in a push-pull manner. Each of the first and second output circuits includes a plurality of output transistors. The cutting circuit is rendered non-conductive when each of the transistors in the first and second output circuits is rendered non-conductive.
US09502079B2
A passive interface for connecting an electronic memory device to an exterior circuit is provided. The passive interface includes a signal connection point, a power connection point and a ground connection point on an electronic memory device. A first passive component forms an electrical connection between the signal connection point and the power connection point. A second passive component forms an electrical connection between the power connection point and the ground connection point. And the power connection point receives a conditioned voltage signal through the electrical connection between the signal connection point and the power connection point. Such a passive interface can be used in a variety of devices, including headsets for intrinsically save applications.
US09502073B2
A non-transitory computer readable medium that stores instructions that cause a computerized system to: process a media stream to extract metadata about characteristics of the media stream; display to a user the metadata; receive from the user an instruction to generate a modified media stream that is responsive to at least one characteristic that is represented by the metadata; and process the media stream to generate a modified media stream, in response to the instruction.
US09502072B2
The present disclosure aims to achieve a more effective image in slow motion. An imaging apparatus of the present disclosure includes an image sensor that outputs image data at a first frame rate and an image processor. The image processor: (i) generates motion image data having a second frame rate that is 1/N of the first frame rate, based on the image data having the first frame rate output from the image sensor, for frames not provided with a given instruction, (ii) generates motion image data having the first frame rate based on the image data having the first frame rate output from the image sensor, for frames provided with a given instruction and (iii) processes the generated motion image data having the first frame rate and the generated motion image data having the second frame rate as a series of motion image data.
US09502057B1
A base plate for a suspension has a swage hub whose inner diameter is offset from the outer diameter, and more specifically, the inner diameter of the swage hub is offset so as to be farther away from the head slider than is the outer diameter. The offset reduces variability in post-swaging deflection of the suspension at the distal end of the base plate to which the load beam is mounted.
US09502055B1
A data storage device may have one or more data writers that are configured with at least one write pole and shield. The write pole and shield can each be positioned on an air bearing surface. The shield may have first and second protrusions each extending from a shield body towards the write pole with the first protrusion positioned on the air bearing surface and the second protrusion separated from the air bearing surface and first protrusion by a lateral notch.
US09502054B2
Devices that include a near field transducer (NFT), the NFT including a peg having five surfaces, the peg including a first material, the first material including gold (Au), silver (Ag), aluminum (Al), copper (Cu), ruthenium (Ru), rhodium (Rh), iridium (Ir), or combinations thereof; an overlying structure; and at least one intermixing layer, positioned between the peg and the overlying structure, the at least one intermixing layer positioned on at least one of the five surfaces of the peg, the intermixing layer including at least the first material and a second material.
US09502038B2
A method and device for voiceprint recognition, include: establishing a first-level Deep Neural Network (DNN) model based on unlabeled speech data, the unlabeled speech data containing no speaker labels and the first-level DNN model specifying a plurality of basic voiceprint features for the unlabeled speech data; obtaining a plurality of high-level voiceprint features by tuning the first-level DNN model based on labeled speech data, the labeled speech data containing speech samples with respective speaker labels, and the tuning producing a second-level DNN model specifying the plurality of high-level voiceprint features; based on the second-level DNN model, registering a respective high-level voiceprint feature sequence for a user based on a registration speech sample received from the user; and performing speaker verification for the user based on the respective high-level voiceprint feature sequence registered for the user.
US09502028B2
Streaming audio is received. The streaming audio includes a frame having plurality of samples. An energy estimate is obtained for the plurality of samples. The energy estimate is compared to at least one threshold. In addition, a band pass estimate of the signal is determined. An energy estimate is obtained for the band-passed plurality of samples. The two energy estimates are compared to at least one threshold each. Based upon the comparison operation, a determination is made as to whether speech is detected.
US09502022B2
A quiet zone generation technique is proposed for interference mitigation for a receive antenna by injecting the very interference signals via iterative processing, generating quiet zones dynamically for receive (RCV) antennas. The receive antenna may feature multiple receiving apertures distributed over a finite area. Optimization loops consist of four cascaded functional blocks; (1) a pick-up array to obtain the interference signals, (2) element weighting and/or repositioning processors, (3) an auxiliary transmit (XMIT) array with optimized element positions, (4) a diagnostic network with strategically located probes, and (5) an optimization processor with cost minimization algorithms. To minimize interferences between transmit (Tx) and receiving (Rx) apertures in limited space of an antenna farm for communications and/or radar applications are very tough problems. However, solutions for co-site interference mitigation may not be generic ones but more specific to geometries of antenna farms, Tx apertures and Rx antenna locations, and beam positions of the Tx beams.
US09502018B2
Systems and methods for notifying game-based clocks and players associated with a sporting event using one or more digital whistles are described. More specifically, the one or more digital whistles, for example used by referees, transmit one or more digital signals upon being used. The transmitted digital signals are received by a whistle processor that processes the transmitted digital signals and transmits instructions to the game-based clocks and players in the sporting event for controlling timekeeping and facilitating a flow of the sporting event.
US09502013B2
A drum tensioning device is provided. The drum tensioning device can include an insert having a flange and a shank. The shank can be configured to engage a tension rod. The tensioning device can also include a casing having a mount configured to receive a connecting member to secure the casing to a shell of the drum. The casing can further include an opening formed in the casing through which the shank of the insert extends and a recess formed on an inner surface of the casing configured to retain the flange of the insert while permitting for radial and axial movement of the shank relative to the opening.
US09502012B2
A percussion device includes a drumstick assembly and a sleeve. The drumstick assembly includes a drumstick having a base and a tip end, and a drumstick tip secured to the tip end of the drumstick, the drumstick tip including a sensor. The sleeve is disposed about at least a portion of the drumstick including the base thereof, and includes at least one control button, a communication element, and a processor in communication with the at least one control button, the drumstick tip and the communication element. The processor is configured to receive a signal from the drumstick tip and to generate output to the communication element. The output so generated includes a signal that specifies a sound file selected by operation of the at least one control button.
US09501997B2
A gate driver (103) and a display device, which relate to the technical field of display, and are applicable to the design and manufacture of display devices. The gate driver (103) comprises: a power-off voltage detection circuit (101) and a power-off de-ghosting function circuit (204) connected to the power-off voltage detection circuit (101), wherein the power-off voltage detection circuit (101) is used for detecting a current voltage state, and outputting a control signal to the power-off de-ghosting function circuit (204) according to the voltage state, so that the power-off de-ghosting function circuit (204) outputs a signal to eliminate power-off ghosting according to the control signal. The gate driver (103) integrates the power-off voltage detection circuit (101) and the power-off de-ghosting function circuit (204); the integration level is high, and the display device can eliminate the power-off ghosting without the need to match the selected type of the gate driver (103) and a printed circuit board.
US09501992B2
An alternating current (AC) light emitting device includes an AC light emitting diode (LED) module and a waveform modulation unit. The AC LED module includes at least two sets of micro-diodes. The waveform modulation unit coupled between the AC LED module and an AC voltage source modulates a waveform of the AC voltage source.
US09501991B1
The present invention provides a scan driving circuit for oxide semiconductor thin film transistors, a pull-down holding circuit part (600) employed in the scan driving circuit for the oxide semiconductor thin film transistors comprises a main inverter and an auxiliary inverter. By introducing a constant low voltage level (DCL) and setting the constant low voltage level (DCL)
US09501989B2
The present invention proposes a gate driver which simplifies a circuit structure by effectively compounding the pull-down holding circuit and signals to achieve a design for ultra-narrow bezel gate driver. In addition, It effectively lessens voltage offset at the second node and prolongs GOA circuit operating time to prolongs lifetime of the LCD when the seventh transistor of the first pull-down holding circuit adopts equivalent diode connection. At last, it reduces RC delay to efficiently lower power-consumption to more effectively decrease LCD energy-consumption when amount of transistors and signals of the first and the second pull-down holding circuits decreases.
US09501979B2
The present invention in its first aspect provides an image display apparatus capable of controlling, for each block obtained by dividing a region of a screen, a backlight emission brightness based on image data of an inputted frame. The image display apparatus includes: a detecting unit that detects a block in which a predetermined object is displayed; a determining unit that determines an object block that is a block in which a background and the predetermined object are displayed based on a detection result by the detecting unit; and a control unit that controls a backlight emission brightness for each block. The control unit approximates a backlight emission brightness of the object block to a backlight emission brightness of another block in which the background is displayed.
US09501967B2
In a display device having a display area in which a plurality of pixels are formed to display an image, each of the plurality of pixels includes a brightness control layer that controls brightness of the pixel by light emission, and a light emission color control layer that controls a light emission color in the pixel by controlling a transmission wavelength band of a light emitted from the brightness control layer to be transmitted, and a light emission color control signal for controlling the transmission wavelength band to control the light emission color in the pixel is input to the light emission color control layer in each pixel.
US09501965B2
An image display apparatus according to the present invention includes: a light-emitting unit capable of separately controlling the emission brightness in each of a plurality of divided regions in a screen; a determining unit configured to determine a target brightness of a predetermined divided region, based on image data corresponding to the predetermined divided region; an estimating unit configured to estimate the brightness of the predetermined divided region when light is emitted by the light-emitting unit at emission brightness which is based on image data in each of the plurality of divided regions; and a control unit configured to control the emission brightness of two or more divided regions including the predetermined divided region based on the difference between the target brightness determined by the determining unit and the brightness estimated by the estimating unit.
US09501961B2
A display panel is disclosed. The display panel includes: at least one first data line, at least one second data line, at least two first pixel columns, and at least two second pixel columns. In two adjacent ones of subpixel rows, the first data line is electrically connected to one of first subpixels in one of the first pixel columns and one of second subpixels in one of the second pixel columns, and the second data line is electrically connected to one of the second subpixels in the one of the second pixel columns and one of the first subpixels in another one of the first pixel columns adjacent to the one of the second pixel columns.
US09501957B2
A reconfigurable label assembly including a container capable of storing or holding a liquid and a front panel, a back panel, a bottom panel, and side panels configured primarily as a label and secondarily as a receptacle capable of holding the liquid separate from the container is presented. In some embodiments, the bottom panel includes a fold. The bottom and side panels are disposed between and substantially parallel to the front panel and back panels in a first configuration to form a label attached to and separable from the container. The front and back panels are separable and the bottom and side panels are expandable to form a receptacle in a second configuration after the label is separated from the container. The side panels include additional folds facilitating transformation from a label to a receptacle and from a receptacle to a label.
US09501950B2
A coach decision support method including collecting sensor data associated with an athlete at a data logger circuitry; wherein sensor data is generated by at least one sensor placed on the athlete; pre-processing the sensor data at the data logger circuitry and filtering sensor noise from the collected sensor data; extracting at least one feature of the collected sensor data; classifying the at least one extracted feature into at least one physical activity; transmitting the physical activity classification to a data analysis module; generating a detailed report of the physical activity analyzing the athlete's performance within a sporting arena; and generating at least one coach decision recommendation based at least in part on the generated detailed report.
US09501949B2
The present specification discloses a method, system and program product that can be used for self-management of any chronic disease. The invention involves the use of a device to enter patient's disease related data. Based on this data patient's habits are detected and presented in a graphical format. The user also has the option of setting up a reminder based on the detected habits.
US09501946B1
Providing haptic feedback to a user over a packet-switched network includes sensing movement of a haptic device by a user, the haptic device being configured to control a first virtual object within a virtual environment, transmitting data associated with the movement of the haptic device from a client computer to a remote server via the packet-switched network, the server modeling movement of the first virtual object in the virtual environment and estimating an orientation and a position of the first virtual object within the virtual environment, the server determining a type of tactile feedback to be provided to the user, the server transmitting the type of tactile feedback data to the client computer via the packet-switched network, and providing tactile feedback to the user with the haptic device.
US09501945B2
An approach is provided for receiving an input for specifying a developmental training activity associated with a user. The approach involves identifying a classification of the developmental training activity as a team activity, an individual activity, or a combination thereof. The approach also involves determining a weighting for the development training activity based on classification. The approach further involves calculating a training score for the user based on the weighting and the developmental training activity.
US09501938B1
A present novel and non-trivial system, device, and method for generating surface information presentable on a display unit is disclosed, where the surface information may be presented to draw a viewer's attention to the presence of threatening object(s). An image generator (“IG”) may be configured to receive navigation data; retrieve object data representative of vertical measurements of objects; and generate an image data set representative of an image comprised of object highlighting band(s) capable of highlighting object(s) which meet object highlighting band criteria, where such criteria could include an object reference. In one embodiment, the object highlighting band could be horizontally-disposed, where the object reference may be a horizontal measurement referenced to aircraft position to which the retrieval of the object data may be limited. In another embodiment, an object highlighting band could be vertically-disposed, where the object reference may be a vertical measurement referenced to aircraft position.
US09501935B2
In an intelligent forward collision warning system that takes into account not only a first preceding vehicle traveling immediately ahead of the ego vehicle but also a second preceding vehicle traveling immediately ahead of the first preceding vehicle, a warning signal is produced upon detecting a critical state of the first or second preceding vehicle or an external condition that is predicted to cause the first preceding vehicle and the ego vehicle to be in a same lane with the first time to collision (TTC) below a prescribed value.
US09501932B2
Disclosed is a vehicular environment estimation device capable of accurately estimating a travel environment around own vehicle on the basis of a predicted route of a mobile object or the like, which is moving in a blind area. A vehicular environment estimation device that is mounted in the own vehicle detects a behavior of another vehicle in the vicinity of the own vehicle, and estimates a travel environment, which affects the traveling of another vehicle, on the basis of the behavior of another vehicle. For example, the presence of another vehicle, which is traveling in a blind area, is estimated on the basis of the behavior of another vehicle. Therefore, it is possible to estimate a vehicle travel environment that cannot be recognized by the own vehicle but can be recognized by another vehicle in the vicinity of the own vehicle.
US09501930B2
A power line proximity sensing and warning system. The embodiments disclosed herein may be configured as standalone systems or may be used in conjunction with each other or with other conventional systems.
US09501921B2
The present invention generally relates to a device that will alert users that they are using (or wasting) more than a certain amount of water. More particularly, the present invention relates to a portable device clip that may be connected to any type of water pipe, will measure and time the flow of water, and will alert users via an audible alarm if and when water flows for more than a user-specified period of time. The invention may be used by both consumers and landlords to educate users in the prevention of undue water consumption, and to save thousands of gallons of water per year.
US09501919B2
Methods and systems for monitoring a subject within a defined spatial environment in order to signal the activity status of subject within the environment to a remote user comprise providing a virtual representation and a virtual model of the subject and the environment respectively. The foregoing can be performed by a camera which is linked to a controller for translating the captured images into virtual versions. The activities of the subject are assigned activity statuses. Hence, assessing the activities of the virtual subject within the virtual environment and comparing this activity to previously assigned statuses provides for determining the activity status of the subject within the environment and communicating this information to a remote user via an interface linked to the controller.
US09501917B2
A monitoring system is disclosed for monitoring and deterring entrance of supervised individuals into an area. The system includes a wearable monitoring device configured to be worn by an individual to be deterred from entrance into a retail environment. The wearable monitoring device includes a theft deterrent device operably configured to be detectable by at least one theft deterrent gate device disposed proximate an entrance area to a retail environment; and an alarm operably configured to communicate an alarm condition in response to the theft deterrent gate device detecting the theft deterrent device.
US09501913B2
A programmable security system and method for protecting an item of merchandise includes a programming station, a programmable key and a security system. The programming station generates a security code and communicates the security code to a memory of the programmable key. The programmable key initially communicates the security code to a memory of the security device and subsequently operates the security device upon a matching of the security code in the memory of the security device with the security code in the memory of the programmable key. The programmable key may also transfer power via electrical contacts or inductive transfer from an internal battery to the security device to operate a lock mechanism. The security code may be communicated by wireless infrared (IR) systems, electrical contacts or inductive transfer. A timer inactivates the programmable key and/or the security device after a predetermine period of time. A counter inactivates the programmable key after a predetermined maximum number of activations.
US09501903B2
Gaming apparatus and methods of conducting a wagering game of chance. A gaming machine is disclosed which is configured for mutually concurrent play of a plurality of games of chance on a single display screen. A method of conducting a wagering activity includes providing a player with a plurality of differing games of chance, at least some of which are mutually concurrently playable on a single screen display of a gaming device and enabling mutually concurrent play of the plurality of differing games of chance on the single screen display. Various other gaming machine configurations and methods of play related to multiple differing games of chance on a single display screen are also disclosed herein. Networked gaming machines are also disclosed.
US09501902B2
Gaming apparatus and methods of conducting a wagering game of chance. A gaming machine is disclosed which is configured for mutually concurrent play of a plurality of games of chance on a single display screen. A method of conducting a wagering activity includes providing a player with a plurality of differing games of chance, at least some of which are mutually concurrently playable on a single screen display of a gaming device and enabling mutually concurrent play of the plurality of differing games of chance on the single screen display. Various other gaming machine configurations and methods of play related to multiple differing games of chance on a single display screen are also disclosed herein. Networked gaming machines are also disclosed.
US09501899B2
A gaming system and method of rewarding players of electronic gaming machines connected by a network to a host computer, including storing player-useable points at a network-accessible location, enabling a player to convert at least some of the points into monetary units at a conversion rate, wherein the monetary units are convertible into credits for wagering on at least one of the electronic gaming machines, awarding a personal points conversion rate multiplier to a player, and applying the points conversion rate multiplier to the conversion rate.
US09501886B2
The invention provides a coin feeder for feeding coins to a coin sensor. The coin feeder comprises a hopper disc having a first surface and arranged to receive coins on the first surface, and to transport the coins along a first path towards the coin sensor. The coin feeder also comprises one or more coin deflectors to deflect coins received on the first surface from the first path if the coins are above a threshold thickness. At least one of the one or more coin deflectors comprises a rotatable member spaced from the first surface.
US09501881B2
Disclosed are an apparatus and a method for managing access to a shared resource based on identity that is established by use of biometric data. A biometric locking device (i.e., a “b-lock”) can be used to restrict access to a shared resource, such as a house, a car, etc. In some embodiments, the b-lock can establish an identity of a user based on biometric data obtained by a biometric sensor of the b-lock, and can register the biometric data. After the biometric data is registered, the user can scan, e.g., his finger using the biometric sensor of the b-lock, and the b-lock can verify that the biometric data obtained based on the scan of the finger matches the registered biometric data. Once verified, the b-lock can unlock a locking mechanism of the b-lock to enable the user to access the shared resource.
US09501877B2
An intelligent towing plug apparatus and software system that performs trailer electrical system testing, diagnostic and monitoring routines as well as towing vehicle plug testing utilizing wireless technology housed completely inside a towing adapter plug or attached towing plug compartment housing that interfaces with any smart phone or towing vehicle on-board computer system that has downloaded or preinstalled the intelligent towing plug mobile application or software compatible with the on-board computer's operating system.
US09501875B2
Computer-implemented methods, systems and apparatus are disclosed for monitoring and reporting notification preferences. A processor of a vehicle determines whether any vehicle events specified in notification preferences have occurred. The notification preferences can be defined by an owner of the vehicle and specify vehicle events that the owner wants to be monitored and reported. When the processor determines that any vehicle event specified in the notification preferences has occurred, the processor can store a record of the vehicle event (and any other vehicle events that occur) in a vehicle event detection log, and then regularly or periodically generate a notification report that includes records for each of the vehicle events that are stored in the vehicle event detection log. The notification report can then be communicated to a remote computer located outside the vehicle. In addition, some vehicle events can trigger generation and communication of an alert message to the remote computer.
US09501868B2
Methods and systems for generating surface data from polygonal data are disclosed. The methods and systems receive polygonal data which describe discrete points on an object. The methods and systems analyze and use the data to calculate and define a continuous BREP object which accurately represents the original polygonal object. In some embodiments, the BREP object is modified and certain details of the modification operations are recorded. The polygonal data may be edited and a new BREP object created based on the edited polygonal data. The new BREP object may be automatically modified by automatically reperforming the recorded modification operations.
US09501864B2
Because using the same number of bits per residual depth offset compression is not the best distribution of bits, the bits per residual may be distributed instead according to the content of the depths of a tile. For example, if the depth differences close to the Zmax are small, then fewer bits can be spent on residuals for the samples that are encoded relative to Zmax. Consequently, more bits can be spent on the residuals for the samples that are encoded relative to Zmin. As a result, more tiles succeed at compressing to the required number of bits.
US09501857B2
A display control method includes: inputting user's image including a drawing portion made by hand drawing and being a display target image; and performing image control including causing the input user's image to emerge from any one of a left end and a right end of a predetermined display region, on which the user's image is to be displayed, and moving the user's image that has emerged.
US09501856B2
An approach is provided for generating panoramic maps with elements of subtle movement. A media platform processes and/or facilitates a processing of one or more panoramic images to cause, at least in part, a segmentation of at least one object from the one or more panoramic images. A media platform then determines one or more animations associated with the at least one object. A media platform thereafter causes, at least in part, a rendering of the one or more panoramic images with the one or more animations substituting for, modifying, or a combination thereof the at least one object.
US09501847B1
One embodiment of the present invention sets forth a technique for computing line stipple using a parallel rasterizer. Stipple phases are computed in parallel for individual line segments of a line strip during the viewport scale, cull, and clipping operations. The line segments are distributed to multiple parallel rasterizers. Each line segment may be sent to only one of the parallel rasterizers. Update phase messages that include an accumulated stipple phase for a batch of line segments are broadcast to all of the multiple parallel rasterizers. The update phase messages are used by the multiple parallel rasterizers to reconstruct the stipple phases for each line segment of a line strip in order to correctly render stippled line strips and produce a continuous stippled line.
US09501837B2
A method and apparatus for unsupervised segmentation of an image is provided. In some exemplary embodiments, the method adjusts a segmentation parameter of a traditional graph-based segmentation algorithm along the image to generate a segmentation map that is perceptually reasonable for a human observer. In some embodiments, the method reduces over-segmentation and under-segmentation of the image.
US09501811B2
The invention notably relates to computer-implemented method for resizing an image I. The method comprises the steps of: providing the image I to resize; and providing an image significance by computing a significance of each pixel in the image to resize. An original spatial domain (Ω) of the significance image is extracted. A transformation Tθ, parameterized as an interpolating spline by a set of control points, is provided from Ω to a resized spatial domain Ω′; subdividing Ω into cells, each cell being defined by a subset of control points of the set. For each cell, a weighted average of the significance of the pixels in the cell is computed, the weighted average being computed using the interpolating spline. The cells of Ω are deformed by displacing one or more control points of the cells having a lesser weighted average. The transformation Tθ over a spatial domain of the image I is computed using the displaced one or more control points. A resized image J is computed by applying the computed transformation Tθ to the spatial domain of the image I to resize.
US09501810B2
This disclosure is directed to a touchless interactive environment. An input device may be configured to capture electronic images corresponding to physical objects detectable within a physical three-dimensional region. A computer system may establish a virtual three-dimensional region mapped to the physical three-dimensional region, with the virtual three-dimensional region defining a space where a plurality of virtual objects are instantiated based on the plurality of electronic images. The computer system may select a virtual object from the plurality of virtual objects as one or more commanding objects, with the one or more commanding objects indicating a command of a graphical user interface to be performed based on a position of the one or more commanding objects. The computer system may then perform the command of the graphical user interface based on the position of the one or more commanding objects.
US09501809B2
A graphics client receives a frame, the frame comprising scene model data. A server load balancing factor is set based on the scene model data. A prospective rendering factor is set based on the scene model data. The frame is partitioned into a plurality of server bands based on the server load balancing factor and the prospective rendering factor. The server bands are distributed to a plurality of compute servers. Processed server bands are received from the compute servers. A processed frame is assembled based on the received processed server bands. The processed frame is transmitted for display to a user as an image.
US09501802B2
Solutions for capturing and displaying conversation history for providing conversation capture functionality. Some such solutions use a user supersystem as a communications hub to capture and/or generate relevant information for enhancing conversations with contacts, including address book information, contact notes, conversation history information, and/or conversation anchors. The information may then be processed for display to the user via a graphical interface.
US09501799B2
Systems and methods are disclosed herein for determining an insurance evaluation based on an industrial classification. The system may be configured to receive an electronic resource address relating to an entity, access data relating to the entity using the electronic resource address, tokenize the data, generate token counts based on the tokenized data; and apply at least one computerized predictive model to the token counts to determine one or more classifications associated with the entity. The system may further be configured to conduct evaluations of insurability, fraud determinations and other processes using the determined classification(s).
US09501792B2
A system and method for a graphical user interface including a multimedia container. The method includes accessing, within a mobile device, a first data store corresponding to a multimedia container and accessing a second data store. The multimedia container comprises a first object and the multimedia container is operable to comprise one or more applications, widgets, and pieces of content. The second data store comprises data corresponding to a first electronic book. The method further includes displaying a first image corresponding to the first object, where the first image comprises a first book cover image corresponding to the first electronic book. The first image further comprises a first statistic corresponding to the first electronic book and the first statistic is related to access of the first electronic book.
US09501788B2
The present disclosure identifies and/or delivers tailored content based upon a service dialog. For example, the systems may receive a request for tailored content, facilitate a service dialog to obtain information related to the request, and communicate a plurality of tailored content based upon the information related to the request. Further, the systems may identify tailored content based upon a consumer profile, communicate the tailored content to a web client, and/or receive a selection of the tailored content. Further still, the systems may modify a magazine (e.g., content that is presented electronically) based upon tailored content.
US09501787B2
The present disclosure identifies and/or delivers tailored content based upon a service dialog. For example, the systems may receive a request for tailored content, facilitate a service dialog to obtain information related to the request, and communicate a plurality of tailored content based upon the information related to the request. Further, the systems may identify tailored content based upon a consumer profile, communicate the tailored content to a web client, and/or receive a selection of the tailored content. Further still, the systems may modify a magazine (e.g., content that is presented electronically) based upon tailored content.
US09501780B2
The present invention is a system and method for conducting survey using wireless devices. The system architecture of the present invention comprises a location server and a location system. The location server can receive a survey request from a subscriber, delineate a survey area for the survey, broadcast a query containing the survey to a plurality of wireless devices, process responses received from the wireless devices, and deliver a result of the survey to the subscriber. The location system can generate location information for each of the wireless devices that received the query. The location system may be a network-based unit or a portable unit provisioned at each of the wireless devices. In one of the embodiments, the location system is a GPS receiver that generates the longitude and the latitude of the wireless devices at which it is provisioned.
US09501776B2
Systems and methods include an input interface that receives registration information including a contact number input into a mobile device of a user, a call interface that transmits a call signal to a call center system, wherein the call signal comprises the call signal contact number that placed a call associated with the call signal and a communication interface that transmits the registration information to a profile database that stores the registration information as a profile for authenticating the mobile device user and identifying information from the mobile device of the user during the call. The call center system includes a call authentication processor that retrieves the user profile, an authentication interface that receives the identifying information, and an authentication processor that compares the identifying information with the user profile, and routes the call on an authenticated call path if the identifying information at least partially matches the user profile.
US09501764B2
A method, system, and computer-program product for communicating within a messaging architecture using a structured data object are disclosed. The method includes identifying a structured data object configured to represent structured data, receiving the structured data at a messaging system, generating a message that includes the structured data, and sending the message. The structured data object is configured to be accessed by an application and the messaging system, and includes a request element and a response element. The sending includes transferring the message via the messaging system.
US09501762B2
Various embodiments of the disclosed technology can obtain information about associations between users (e.g., user accounts) of a content management system and applications compatible with the content management system. Various embodiments can also obtain information about a plurality of attributes associated with usage of the content management system by the users (e.g., user accounts). In some embodiments, the attributes can include a device property, a usage pattern, an account property, a content item property, a profile property, a preference property, or a domain property. Moreover, data about social connections of the users (e.g., user accounts) can also be obtained. Based, at least in part, on at least one of the information about the associations, the information about the plurality of attributes, or the data about the social connections, one or more applications can be recommended to a selected user (e.g., a selected user account).
US09501761B2
A computer-based investigative analysis system is disclosed in which a user can share results of an investigation with other users in a way that allows the sharing user to visualize how the results will be shared before they are shared. The results are shared in the form of a visual graph having nodes, edges, and other presentation elements. The nodes represent data objects that are the subject of the investigation and the edges represent connections between the data objects. The graph is shared in the form of an automatically generated redacted graph omitting nodes, edges, and presentation elements for which the other users do not have permission to view. Before sharing the graph, the sharing user is presented with a visualization of the automatically generated redacted graph providing the user an opportunity to confirm that sharing the redacted graph will not constitute an unauthorized information leakage.
US09501758B2
A system that incorporates teachings of the present disclosure may include, for example, a system having a controller to present an overlay that is combined with a presentation of media content, collect one or more user-generated remarks from each of a plurality of computing devices where the one or more user-generated remarks are temporally associated with media content presented at the plurality of computing devices according to the overlay, monitor one or more user-generated comments from each of the plurality of computing devices, and selectively filter the one or more user-generated comments from each of the plurality of computing devices. Other embodiments are disclosed.
US09501756B2
A method for managing an inventory system includes receiving an operation request that identifies an inventory item and selecting, from a plurality of workstations, a workstation at which to fulfill the operation request. The method also includes moving an inventory holder storing the identified inventory item to the selected workstation and moving a supply holder storing a supply item associated with the received operation request to the selected workstation. The method additionally includes fulfilling the operation request, at least in part, at the workstation.
US09501744B1
In one embodiment, a method includes providing an a priori classification engine, an a posteriori classification engine, and a heuristics engine. The a priori classification engine is operable to perform an a priori classification. The a posteriori classification engine is operable to perform an a posteriori classification. The heuristics engine is operable to perform a heuristics classification. In addition, the method includes accessing data from at least one source. The method further includes, responsive to an indication that the a priori classification should be performed, performing the a priori classification on the data. The method also includes, responsive to an indication that the a posteriori classification should be performed, performing the a posteriori classification on the data. Further, the method includes, responsive to an indication that the heuristics classification should be performed, performing the heuristics classification on the data.
US09501741B2
A method and apparatus are provided for building an intelligent automated assistant. Embodiments of the present invention rely on the concept of “active ontologies” (e.g., execution environments constructed in an ontology-like manner) to build and run applications for use by intelligent automated assistants. In one specific embodiment, a method for building an automated assistant includes interfacing a service-oriented architecture that includes a plurality of remote services to an active ontology, where the active ontology includes at least one active processing element that models a domain. At least one of the remote services is then registered for use in the domain.
US09501740B2
This disclosure generally describes methods and systems, including computer-implemented methods, computer-program products, and computer systems, for predicting well markers. One computer-implemented method includes separating neural-network (NN)-predicted facies output associated with a plurality of wells into two sets, a first set of NN-predicted facies output of training wells and a second set of NN-predicted facies output of target wells, calculating, for each training well of the plurality of wells, a sameness score between zones of NN-predicted facies output and human-identified lithostratigraphic units (finer zones), calculating a mean sameness score for the finer zones for all training wells, identifying finer zones with a mean sameness score greater than a threshold value as dominant facies zones, and iterating over each target well to calculate a top and depth position of each dominant facies zone determined based upon the NN-predicted facies output of the target well.
US09501738B1
A cellular computational platform is disclosed that includes a multiplicity of functionally identical, repeating computational hardware units that are interconnected electrically and optically. Each computational hardware unit includes a reprogrammable local memory and has interconnections to other such units that have reconfigurable weights. Each computational hardware unit is configured to transmit signals into the network for broadcast in a protocol-less manner to other such units in the network, and to respond to protocol-less broadcast messages that it receives from the network. Each computational hardware unit is further configured to reprogram the local memory in response to incoming electrical and/or optical signals.
US09501736B2
A breakaway RFID tag is configured such that it comprises part of a Printed Circuit Board Assembly (PCB). Thus, the breakaway RFID tag can be used to track the PCB as it migrates through a manufacturing process. In one embodiment, the RFID tag can be assembled first and then used to track the PCB as it is populated with components and installed into larger assemblies and ultimately into the end device. Once the PCB is installed into a larger assembly or the end device, the breakaway RFID tag is configured such that it can be broken off and attached to the outside of the larger assembly or end device.
US09501735B2
A wearable device includes a wearable device structure at least partially made of a silicone rubber. A support member is at least partially positioned in the wearable device structure. ID circuitry is at least partially positioned and coupled to the support. One or more batteries coupled to the ID circuitry.
US09501734B2
An RFID tag for location inside a tubular base portion of a freestanding cryogenic vial, the RFID tag comprising: an RFID chip; an antenna connected to the chip; a support medium configured to support the chip and connected antenna; and a plug at least partially surrounding the chip, the antenna and the support medium, the plug being shaped to engage the tubular base portion of the vial. The RFID tag may be used to retrofit vials already stored at cryogenic temperatures.
US09501730B2
Barcodes are provided that are applied to or integrated with a moving carrier, where the barcodes have a plurality of information modules, at least one clock track having a plurality of alternating clock track modules and at least one reference track having a plurality of alternating reference track modules, where the at least one reference track is a second clock track and has a same periodicity as the clock track but a spatial phase shift when compared to the clock track. The barcode is configured to allow at least one barcode reader to determine a direction of movement of the carrier from at least one signal from a clock track detector and at least one signal from a reference detector.
US09501724B1
A convolutional neural network (CNN) is trained for font recognition and font similarity learning. In a training phase, text images with font labels are synthesized by introducing variances to minimize the gap between the training images and real-world text images. Training images are generated and input into the CNN. The output is fed into an N-way softmax function dependent on the number of fonts the CNN is being trained on, producing a distribution of classified text images over N class labels. In a testing phase, each test image is normalized in height and squeezed in aspect ratio resulting in a plurality of test patches. The CNN averages the probabilities of each test patch belonging to a set of fonts to obtain a classification. Feature representations may be extracted and utilized to define font similarity between fonts, which may be utilized in font suggestion, font browsing, or font recognition applications.
US09501715B2
The present invention discloses a method for detecting a salient region of a stereoscopic image, comprising: step 1) calculating flow information of each pixel separately with respect to a left-eye view and a right-eye view of the stereoscopic image; step 2) matching the flow information, to obtain a parallax map; step 3) selecting one of the left-eye view and the right-eye view, dividing it into T non-overlapping square image blocks; step 4) calculating a parallax effect value for each of the image blocks of the parallax map; step 5) for each of the image blocks of the selected one of the left-eye view and the right-eye view, calculating a central bias feature value and a spatial dissimilarity value, and multiplying the three values, to obtain a saliency value of the image block; and step 6) obtaining a saliency gray scale map of the stereoscopic image from saliency values of the image blocks. The present invention provides a method for extracting stereoscopic saliency based on parallax effects and spatial dissimilarity, acquiring depth information by utilizing parallax, and combining visual central bias feature and spatial dissimilarity to realize more accurate detection of a stereoscopic salient region.
US09501711B2
The present invention is a method including: correcting difference between a pixel statistical value of a specific layer and a pixel statistical value of a layer that is wider than the specific layer using an edge information of a layer that is wider than the specific layer; correcting the pixel statistical value of the specific layer using post-correction difference and the pixel statistical value of layer that is wider than the specific layer; recorrecting the post-correction pixel statistical value of the specific layer using difference between a pre-correction pixel statistical value of the specific layer and the post-correction pixel statistical value of the specific layer and the edge information of a layer that is wider than the specific layer; and correcting the target pixel by repeating correction and recorrection until the layer reduces its range from the maximum range to the minimum range.
US09501708B1
A text-recognition system and method include a trained classifier configured to identify a font of a frame of text line image. The system also includes an adaptive sliding window configured to divide the frame into a plurality of cells. A first cell is located around a prominent writing line of the text line image. Additional cells are located above the prominent writing line and below the prominent writing line, such that each of the additional cells above the prominent writing line has a same percentage of ink-pixels and each of the additional cells below the prominent writing line has a same percentage of ink-pixels. The system also includes a font-specific feature parameters database configured for extraction of text features from each of the cells. The system also includes one or more trained font-specific recognizers configured to recognize the extracted text features using an associated font-specific recognizer for the identified font.
US09501706B2
This disclosure describes systems, methods, and computer-readable media related to employing adaptive multi-feature semantic location sensing methods to estimate the semantic location of a mobile device. An image of a transaction document may be captured. The captured image to a processing server for processing magnetic ink character recognition (MICR) information from the captured image of the transaction document may be transmitted. A processing result of processing the MICR information from the captured image of the transaction document may be received. The processing result of the MICR information with the captured image of the transaction document may be compared. In response to the comparison, the MICR information to a payment verification server may be submitted for verification.
US09501704B2
A drowsiness estimation device comprises an imaging unit 1, a regional temperature calculation unit 6, and a weighted subtraction unit 7. The imaging unit 1 obtains visible spectrum image data in a visible spectrum capture mode and obtains infra-red image data indicating a surface body temperature distribution for a subject's body in an infra-red capture mode. The regional temperature calculation unit 6 detects a temperature of an ocular center region within the surface body temperature distribution indicated by the infra-red image data. The weighted subtraction unit 7 applies a correction to a temperature parameter for drowsiness estimation, based on the detected ocular center region temperature. A drowsiness estimation for the user is then performed according to the corrected parameter.
US09501694B2
Methods and devices provide a quick and intuitive method to launch a specific application, dial a number or send a message by drawing a pictorial key, symbol or shape on a computing device touchscreen, touchpad or other touchsurface. A shape drawn on a touchsurface is compared to one or more code shapes stored in memory to determine if there is a match or correlation. If the entered shape correlates to a stored code shape, an application, file, function or keystroke sequence linked to the correlated code shape is implemented. The methods also enable communication involving sending a shape or parameters defining a shape from one computing device to another where the shape is compared to code shapes in memory of the receiving computing device. If the received shape correlates to a stored code shape, an application, file, function or keystroke sequence linked to the correlated code shape is implemented.
US09501692B2
According to one aspect of the teachings presented herein, a projective volume monitoring apparatus is configured to detect objects intruding into a monitoring zone. The projective volume monitoring apparatus is configured to detect the intrusion of objects of a minimum object size relative to a protection boundary, based on an advantageous processing technique that represents range pixels obtained from stereo correlation processing in spherical coordinates and maps those range pixels to a two-dimensional histogram that is defined over the projective coordinate space associated with capturing the stereo images used in correlation processing. The histogram quantizes the horizontal and vertical solid angle ranges of the projective coordinate space into a grid of cells. The apparatus flags range pixels that are within the protection boundary and accumulates them into corresponding cells of the histogram, and then performs clustering on the histogram cells to detect object intrusions.
US09501688B2
An apparatus includes a detection unit configured to detect an object from image data, and a processing unit configured to perform processing for the object detected by the detection unit. The detection unit includes a first detection unit and a second detection unit having a detection tolerance wider than that of the first detection unit, and the object is detected by selecting the first detection unit or the second detection unit in accordance with the contents of the processing to be performed by the processing unit.
US09501686B2
An optoelectric sensor, comprising: a light-sensitive structure which comprises a substrate and an array of pixel cells located on the substrate, wherein each of the pixel cells comprises a thin film transistor and a photodiode; a fiber optical guide plate located above the light-sensitive structure, which comprises a group of optical fiber bundles configured to be perpendicular to the substrate, and each of the optical fiber bundles has an diameter smaller than or equal to a width of pixel cell; and a backlight source located below the light-sensitive structure. The fiber plate will enable each pixel cell detecting features of an object surface corresponding thereto more independently, so as to improve the resolution of the optoelectric sensor. The optical fiber bundles are configured to be perpendicular to the substrate, and the optoelectric sensor will have a thin structure.
US09501680B2
Methods and devices for batch scanning 2D barcodes are provided by using a 2D barcode positioning process to determine a barcode area corresponding to each 2D barcode of a plurality of 2D barcodes in an image. According to the barcode area corresponding to each 2D barcode, the image containing the plurality of 2D barcodes can be segmented to provide a plurality of 2D barcode images with each barcode image corresponding to one 2D barcode of the plurality of 2D barcodes. Each barcode image of the plurality of 2D barcode images corresponding to the plurality of 2D barcodes can be decoded to obtain data contained in each barcode image. An exemplary device can include a positioning module, a segmenting module, and a decoding module.
US09501676B2
A data management device configured to manage data stored in a contactless storage medium mounted to an electronic apparatus has a data storage unit that stores a plurality of data units including information of the electronic apparatus, a state detection unit that detects a state of the electronic apparatus, a data selection unit that, by referring to selection rules associating states of the electronic apparatus with types of the data, selects data comprising information conforming with the electronic apparatus under a state detected by the state detection unit from the data storage unit, and a data management unit that stores the data selected by the data selection unit in the contactless storage medium.
US09501675B1
A Radio Frequency Identification (RFID) reader containing a reader key authenticates an RFID tag containing a tag key by receiving a tag identifier from the tag; challenging the tag with a tag challenge; receiving a tag response based at least on the tag challenge and the tag key but not including the tag key; sending a second message including at least the tag identifier and the tag response to a verification authority; and receiving a reply from the verification authority. The reader and the verification authority may mutually authenticate each other before, during, or after the tag authentication process. The verification authority may notify a designated party if a response is incorrect.
US09501658B1
A method, system and computer program product for protecting access to a computer file are disclosed. In embodiments, the method comprises a user, employing a user computer, selecting a file, and creating a reference file to protect access to this selected file. When a requester uses a computer device to request access to the protected file, the reference file initiates a procedure to determine if the computing device is entitled to access the protected file by validating a series of computer components that uniquely identify the computing device. In embodiments, a set of specified computer configuration data is stored in a specified storage location; and the series of computer components that uniquely identify the computing device are validated by comparing this set of computer configuration data with the series of computer components that uniquely identify the computing device.
US09501656B2
A global policy is applied to only select resources (e.g., certain file folders) based on property settings associated as metadata with those resources. The resource property settings correspond to a defined property set (e.g., a global taxonomy) that is consistent with the global policy. When global policy is received, the property metadata for each resource determines whether to apply the global policy to that resource. In this way, a central administrator may provide the defined property set, a policy author may provide the policy, and a local administrator may set the resource property settings.
US09501650B2
The present disclosure provides a system that includes a server hosting an application under test (AUT), an observer configured to monitor instructions executed by the AUT, and a computing device communicatively coupled to the AUT and the observer through a common communication channel. The computing device may be configured to send an application request to the AUT, wherein the application request is configured to expose a potential vulnerability of the AUT. The computing device may receive an application response from the AUT in accordance with the AUT's programming. The computing device may send a service request to the observer, and receive a service response from the observer that contains information corresponding to the instructions executed by the AUT due to the application request, information about the AUT, or information about a server hosting the AUT.
US09501646B2
A necessary information extraction unit extracts, from variables used in a target program, an output variable to which output information to be output by an output function defined in an output function list is set. The necessary information extraction unit extracts, from the variables used in the target program, an encryption variable to which encrypted information encrypted by an encrypting function defined in an encryption function list is set. A protected state analysis unit refers to an assignment statement included in the target program, and extracts an encrypted state variable to which the encrypted information is assigned. A vulnerability determination unit determines whether or not the encrypted state variable and the output variable are the same variable, and outputs a program verification result based on a result of determination.
US09501640B2
In accordance with one embodiment of the present disclosure, a method for determining the similarity between a first data set and a second data set is provided. The method includes performing an entropy analysis on the first and second data sets to produce a first entropy result, wherein the first data set comprises data representative of a first one or more computer files of known content and the second data set comprises data representative of a one or more computer files of unknown content; analyzing the first entropy result; and if the first entropy result is within a predetermined threshold, identifying the second data set as substantially related to the first data set.
US09501637B2
Technologies for shadow stack support for legacy guests include a computing device having a processor with shadow stack support. During execution of a call instruction, the processor determines whether a legacy stack pointer is within bounds and generates a virtual machine exit if the legacy stack pointer is out-of-bounds. If not out-of-bounds, the processor pushes a return address onto the legacy stack and onto a shadow stack protected by a hypervisor. During execution of a return instruction, the processor determines whether top return addresses of the legacy stack and the shadow stack match, and generates a virtual machine exit if the return addresses do not match. If the return addresses match, the processor pops the return addresses off of the legacy stack and off of the shadow stack. The stack out-of-bounds and the stack mismatch virtual machine exits may be handled by the hypervisor. Other embodiments are described and claimed.
US09501636B1
In an approach for changing a password. Aspects of an embodiment of the present invention include an approach for changing a password, wherein the approach includes a processor identifies a resource protected by a password. A processor discovers at least one information source containing information relevant to a process for changing the password of the resource. A processor constructs a set of procedures to change the password using the information relevant to the process for changing the password. A processor alters the password of the resource according to the constructed set of procedures.
US09501617B1
Systems and methods that allow transfer criteria to be defined based on one or more of several attributes, such as a particular user, site, or device, as well as whether individual images and/or image series are classified as thin slices, and applied to medical images in order to determine which images are downloaded, viewed, stored, and/or any number of other actions that might be performed with respect to particular images.
US09501608B1
Examples of techniques for analyzing and generating timing reports for circuits are described herein. A computer-implemented method includes splitting a netlist or cross section of a circuit into sub-circuits. The method further includes building a timing graph by combining generated timing models of the sub-circuits. The method includes determining a full set of dependencies based on each sub-circuit's dependent configuration parameters. The method also further includes generating a sample plan for each sub-circuit. The method includes receiving results from a simulation for each sub-circuit based on the sample plan for each sub-circuit. The method includes generating algebraic forms for an early delay, a late delay, and a slew by curve fitting across the configuration parameters. The method includes propagating arrival times and slew in algebraic forms throughout the timing graph. The method includes evaluating checks based on selected projections from the timing graph to find a worst slack configuration.
US09501607B1
A computing device for a generating composite view for an intellectual property (IP) core may obtain constraints for multiple application specific integrated circuits (ASIC) designs in which the IP core is used; and determine composite constraints for the IP core based on the constraints for the multiple ASIC designs. The composite constraints may be within all constraints for the multiple ASIC designs. A freedom of change to update the particular IP core may be identified based on the composite constraints.
US09501606B2
A method of optimizing timing performance of an IC design is provided. The IC design is expressed as a graph that includes a plurality of nodes representing IC components. The method identifies several paths in the graph that each starts from a timed source node and ends to a timed target node. Each path includes several clocked elements and several computational elements. The method optimizes the timing performance of the IC design by skewing clock signals to one or more clocked elements to satisfy a set of timing constraints. For each identified path, the method determines the ratio of signal travel time from the source node to the destination node to a maximum time allocated for the data signal to travel from the source node to the target node. When the IC design fails timing constraints, the path that has a maximum determined ratio as a cause for timing failure.
US09501605B1
This application relates to a method of routing circuit paths of an integrated circuit, IC. The IC comprises a plurality of circuit elements and a plurality of circuit paths connecting the circuit elements. The method comprises steps of: receiving a representation of the IC, comparing, based on the representation, the circuit elements of the IC against a set of reference circuit elements, classifying the circuit paths of the IC into a plurality of categories based on a result of the comparison, and routing the circuit paths of the IC in accordance with their respective categories. The application further relates to a computer-readable storage medium comprising a computer program that makes a computer perform the steps of said method when executed and to an apparatus for routing circuit paths of an IC.
US09501604B1
A method of testing a circuit design includes generating, for each net of each critical path in the circuit design, a respective ring oscillator circuit design. The ring oscillator circuit design has a source gate coupled to a destination gate via the net and a feedback path that couples an output pin of the destination gate to an input pin of the source gate. Configuration data are generated to implement a respective ring oscillator circuit from each ring oscillator circuit design, and a programmable integrated circuit is configured with the configuration data. The method determines a delay of the net of each ring oscillator circuit.
US09501598B1
A system and method for managing analog assertion publication and re-use for analog and mixed-signal circuit designs. A graphical user interface based environment allows circuit designers to create, verify, formalize, and publish an analog assertion for a circuit design for subsequent re-use with another circuit design. Embodiments enable analog assertion handling while simultaneously depicting a circuit design in a schematic and/or layout editor window. Embodiments capture referenced circuit objects and parameterize the assertion for numerical values and connectivity. A designer may publish the assertion and annotate it with descriptive metadata, possibly with other assertions of related functionality, to a library accessible by users of analog design and verification tools. Another designer may re-use the assertion by searching for and selecting a relevant published assertion, instantiating and binding the selected assertion to specific elements of a second circuit design, and verify the assertion for the second circuit design.
US09501597B2
A method for equivalence checking includes obtaining a first and a second representation for a semiconductor design and applying a set of inputs to both representations. The outputs of the first representation are compared to the outputs of the second representation. If a mismatch is found, the starting states for the first and second representations are evaluated using a model checker to see if they are reachable from a known legal state such as reset state for that representation. If both of the starting states are reachable, the mismatch is a real mismatch providing a counter-example of the equivalence of the two representations. If one or both of the starting states are unreachable, the mismatch is a spurious mismatch and the model checker can be used to generate an invariant to preclude those starting states in future iterations of the equivalence checker.
US09501593B2
A semiconductor device design method includes generating a layout of a semiconductor device based on schematic data. The layout includes location data for at least one electrical component. The method includes receiving first voltage data associated with at least one electrical component. The method includes receiving second voltage data based on simulation results for the semiconductor device. The method includes incorporating, based on the location data of the at least one electrical component, the first voltage data or the second voltage data in the layout to generate a modified layout. The first voltage data or the second voltage data being incorporated in at least one marker layer of the modified layout. The method includes performing a voltage-dependent design rule check (VDRC) on the modified layout. The VDRC analyzes spacing rules associated with the at least one electrical component based on the first voltage data or the second voltage data.
US09501587B2
The disclosure provides a method for pushing association knowledge, comprising: determining ID information of a user when the user accesses resources; retrieving knowledge having ID information coincident with the ID information of the user in the resources; and pushing knowledge with the highest weight among the retrieved knowledge to the user. The disclosure also provides a device for pushing association knowledge, comprising: an ID module configured to determine ID information of a user when the user accesses resources; a retrieval module configured to retrieve knowledge having ID information coincident with the ID information of the user in the resources; and a pushing module configured to push knowledge with the highest weight among the retrieved knowledge to the user. According to the disclosure, it is able to improve the user experience.
US09501580B2
Embodiments of the present invention provide systems and methods for automatically identifying content that may be interesting visitors of a website in the absence of any information on the visitors' interest or preferences.
US09501579B2
The disclosed embodiments provide a system that facilitates access to content. During operation, the system tracks a content item at an online content management system using an identifier for the content item. Next, the system uses the identifier to provide a link to the content item, wherein the link enables access to the content item from an electronic device independently of a location of the content item within the online content management system.
US09501573B2
Personal companions crowd-source and/or crowd-share characterizations, and optionally raw data, from real-world, virtual and/or mixed-reality experiences. Characterizations can advantageously be stored in one or more self-evolving, structured databases, and can be organized according to objects, actions, events and thoughts. Characterizations can be weighted differently for different users, and “forgotten” over time, especially in favor of maintaining higher level characterizations. Personal companions can be used to obtain additional information, and conduct interpersonal, commercial, or other interactions or transactions.
US09501571B1
A system and computer-implemented method are provided for associating categories with business names for generalizing search queries, the method including identifying one or more businesses within a first geographic region, determining a business name and one or more categories for each of the one or more businesses, generating one or more name components for each of the one or more businesses from the name of the business, generating one or more name component groups from the name components of the one or more businesses, each name component group including one or more identical name components, determining for each name component group, if the one or more name components within the name component group are associated with businesses that share one or more common categories and associating the one or more common categories with the name component of the name component group.
US09501562B2
In one aspect, the description relates to identifying complementary data objects, including providing a plurality of data objects, applying a clustering algorithm for grouping at least some of the data objects into two or more clusters, for each of the clusters, calculating a cluster center, calculating, for at least a first one of the cluster centers, a complementary cluster center, determining a second cluster center of a second cluster, the second cluster center being determined as the one of the cluster centers having the smallest distance in respect to the complementary cluster center, selecting at least one data object of the determined second cluster. Other features and aspects may be realized, depending upon the particular application.
US09501551B1
A categorization service is described that automatically categorizes items of interest to a user. The user may possess an item that they wish to offer for sale using the network-based service. The user may prepare an electronic description of the item and submit this item information to a categorization service for categorization. Upon receipt, the categorization service may compare the item information to item category descriptions representing item categories of the network-based server in order to determine category recommendations for the item of interest. The recommended categories are returned to the user to enable the user to assign a category, selected from the category recommendations, to the item of interest.
US09501549B1
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for scoring criteria for content items. In one aspect, a method includes identifying a primary ranking signal and a set of auxiliary ranking signals for ranking a set of criteria for a content item. A primary score and a set of auxiliary scores can be identified for each particular criterion in the set of criteria. Each auxiliary score can be adjusted to generate adjusted auxiliary scores. The adjusting can include applying, to at least a portion of the auxiliary scores, a transformation function that reduces an amount of skewness among the auxiliary scores. A ranking score can be determined for each particular criterion based on a function of the primary score for the particular criterion and the adjusted auxiliary scores.
US09501541B2
A method for POD provisioning and service provisioning is disclosed. The method may comprise storing, by a cloud infrastructure system, subscription order information from a customer identifying a service from a set of cloud services provided by the cloud infrastructure system, the cloud infrastructure system comprising one or more computing devices, wherein the subscription order information includes customer-specific configuration. Additionally, the method may comprise determining, by a computing device from the one or more computing devices, a service associated with the subscription order information. Moreover, the method may comprise mapping a pre-provisioned anonymous deployment to the subscription order information, wherein the pre-provisioned anonymous deployment is specifically pre-provisioned for the determined service. Furthermore, the method may comprise creating, by a computing device from the one or more computing devices, a service instance specifically for the customer by configuring the pre-provisioned anonymous deployment with the customer-specific configuration.
US09501539B2
A method and system for harmonizing and mediating ontologies to search across large data sources is disclosed. The method comprises receiving a query targeting a first ontology. The method further comprises translating the query into one or more translated queries, each translated query targeting a respective ontology different from the first ontology. For each of the queries, issuing the query to a respective database organized according to the respective ontology of the query, and receiving a respective result set for the query, wherein the respective result set corresponds to the respective ontology of the query. The method further comprises translating the respective result set into a translated result set corresponding to the first ontology, aggregating the result sets into an aggregated result set corresponding to the first ontology, and returning the aggregated results set corresponding to the first ontology.
US09501536B1
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating query plans for queries that include common expressions. One of the methods includes receiving an initial query plan generated for a query that includes multiple common expressions; identifying two or more matching subtrees of the initial query plan; generating an alternative query plan that includes a CTE producer operator and having an instance of one of the matching subtrees as one or more descendant operators of the CTE producer operator, including replacing at least one instance of a matching subtree in the initial query plan with a CTE consumer operator corresponding to the CTE producer operator; computing respective costs for the initial query plan and the alternative query plan; selecting the alternative query plan based on the cost for the alternative query plan; and computing a result for the query using the alternative query plan instead of the initial query plan.
US09501530B1
Systems and methods of the disclosure relate to selecting content via a computer network. The system can receive a query to generate content selection criteria. The system can identify an entity of the query and a query graph based on the entity. The system can access a database to identify a template corresponding to the query graph. The template can include a topology and a named variable. The system can determine multiple semantic criteria corresponding to the named variable that match the query graph. The system can use a statistical metric of each of the matching semantic criteria to select candidate content selection criteria.
US09501529B2
According to one embodiment of the present invention, a system searches content managed by a search engine. The system receives a relational database type query, translates the relational database type query into a query for the search engine, and submits the translated query to the search engine to retrieve information. The system formats resulting information from the search engine into a relational database query result set. Embodiments of the present invention further include a method and computer program product for searching content managed by a search engine in substantially the same manners described above.
US09501521B2
Techniques provided herein allow for estimating data missing in query results provided in response to queries performed on data managed by a data management system. In the event that one or more leaf nodes are unable or unavailable to process a query, a final query result provided in response to the original query may be missing data that exists on those leaf nodes. A data accounting service monitors what managed data is being stored on the leaf nodes and on what leaf node. The data accounting service can estimate how much data is missing from a final query result when one or more of the leaf nodes are unable or unavailable to process a query.
US09501520B2
Disclosed is an information processing apparatus, an information processing method, and a program storage medium which can present associated information related to a document to be processed to a user. An accumulation block accumulates a database of associated information. A presentation block presents to the user the associated information corresponding to the document to be processed at occurrence of an event. An agent control block controls the manner of displaying an agent for example.
US09501519B1
A graphical item chooser sorts candidate products or services by initially classifying each of one or more objective icons as a primary objective icon or a secondary objective icon. Each objective icon represents one or more desired characteristics of a product or service that facilitates a particular objective. The graphical item chooser may further determine at least one most desired characteristic of the ideal product or service. The determination is made based on a frequency that each desired characteristic is represented by the one or more objective icons. Having made the determination, the graphical item chooser then sorts the candidate products or services based at least on similarities between one or more characteristics of each candidate product or service and the at least one most desired characteristic. Following the sort, the graphical item chooser generates a sorted list of suitable products or services.
US09501518B2
This disclosure relates to improving the efficiency and quality of real-time extracting, transforming, and/or loading data using customer information control system (CICS) interval control element (ICE) chain processing.
US09501511B2
A content preview of a content item stored in an online storage system can be viewed on a client device without the content item itself being downloaded to the client device and without the use of software associated with the content item being installed on the client device. Furthermore, data storage and processing requirements can be minimized by creating and storing only one content preview for each unique content item. The content item can be identified by using the content item as a hash key in a hashing algorithm. The resulting unique identifier can be used to search a preview index that lists all created content previews and their location. A content preview is only created if one does not exist. The unique identifier can be used to locate the content preview and return it in response to a preview request by a client device.
US09501496B2
Presenting database items includes providing a plurality of clusters, where each of the clusters is formed by grouping database items according to location information associated therewith, creating a plurality of geographic elements based on the clusters, and presenting the geographic elements to a user using a note atlas that represents all of the geographic elements corresponding to a set of the database items, where indicators of corresponding clusters are provided with each of the geographic elements. A quantity of database items may be provided with each of the corresponding clusters. The note atlas may show at least two levels of detail corresponding to a world level of detail, a points of interest level of detail and a city level of detail. Points of interest may be determined by having a user provide points of interest on a map.
US09501494B2
Systems and methods for structuring information include determining information quantity (IQ) and information value (IV) in an original digital information file (ODIF). An initial manipulation process applied to the ODIF forms a first resulting DIF (FRDIF), and a subsequent manipulation process applied to the FRDIF forms a second resulting DIF, wherein each manipulation process removes at least one element of the processed DIF and/or represents an element combination with a representative element and a first indicia of an interrelationship between the representative element and one or more elements in the combination, to reduce the IQ of the processed DIF, while retaining the IV thereof within a threshold. Manipulation processes are successively applied to the previously resulting DIF until successive applications do not achieve a threshold reduction in IQ. The last resulting DIF has a primary structure with a reduced IQ and an IV within the threshold of the original IV.
US09501492B2
A method and system for a combined journaling and non-journaling file system is disclosed. In the present invention, data is stored on a first storage media using a first device in a format associated with a file system, wherein the file system is a non-journaling file system. Journal information associated with the file system is stored on a second storage media in the first device, wherein the journal information is distinct from the file system and the data is readable by other devices having a file system compatible with the file system.
US09501484B2
Recognizing cloud content techniques are described herein. A designated storage location for cloud content corresponding to a service is registered locally at a device. Files stored in association with the registered storage location may be recognized as cloud content of the corresponding service. The recognized cloud content may be handled in various ways to customize the user experience and tailor interaction with cloud content. For example, icons or other visual identifiers may be used within device, operating system and/or application user interfaces to represent an association of files with a particular service based on recognition of the files as cloud content. Additionally, a registered storage location for a device may be employed to obtain relative paths to files that may be used to roam file activity lists between different devices.
US09501483B2
A key-value store provides column-oriented access to data in a distributed and fault tolerant manner. Data can be inserted into the data store and data can be retrieved either randomly or sequentially from the data store at high rates. Keys for a table are ordered and the entire table is divided into key ranges. Each key range is handled by a table which itself is divided into key ranges called a partition. Partitions are also divided into segments. Such recursive division into smaller and smaller key ranges provides parallelism. At the highest level, operations on tablets can be distributed to different nodes. At lower levels, different threads can handle operations on individual segments. Large-scale restructuring operations can be decomposed into operations on individual segments so that a global lock on larger objects does not need to be kept across the entire operation.
US09501481B2
A content stream including content items retrieved from various applications executing on a client device is presented by the client device. A set of content items associated with a topic matching a stream topic associated with the content stream is identified from the retrieved content items. Quality scores are determined for each content item in the set providing a measure of a user's interest in each content item. A display set of content items is selected based on the quality scores, with one or more content items from the display set displayed based on a stream template. The stream template includes multiple slots each associated with one or more content items, and specifies a relative position of different slots to each other.
US09501478B2
A method includes accessing, at a device, data identifying a plurality of categories of media content. The data includes a first value associated with a first category of the plurality of categories of media content and a second value associated with a second category of the plurality of categories of media content. The method also includes modifying the data to remove the first category in response to determining that the first value does not satisfy a threshold. The method further includes adjusting the second value after modifying the data to remove the first category.
US09501466B1
A system for identifying address components includes a training address interface, a training address probability processor, a parsing address interface, and a processor. The training address interface is to receive training addresses. The training addresses are a set of components with corresponding identifiers. The training address probability processor is to determine probabilities of each component of the training addresses being associated with each identifier. The parsing address interface to receive an address for parsing. The processor is to determine a matching model of a set of models based at least in part on a matching probability for each model for a tokenized address, which is based on the address for parsing, and associate each component of the tokenized address with an identifier based at least in part on the matching model.
US09501458B2
A browser-executable software program for presenting a web page that provides the “look and feel” and functionality of a mobile application can be automatically generated from a mobile application specification. The mobile application specification identifies one or more predetermined content component types and one or more associated content sources. For each content component type, a copy of a corresponding code generation template is populated with a URL for each corresponding content source and executed to produce browser-executable program code. The browser-executable program code is then embedded into a populated copy of a navigation container code template to form a complete browser-executable software program, which is integrated into an HTML page. The HTML page can be returned in response to a request from a browser executing on a networked mobile wireless telecommunication computing device and the HTML page carries the browser-executable software program to the browser.
US09501457B2
Methods, systems, and apparatuses, including computer programs encoded on a computer storage medium, for creating a communication including content editable in a browser independent of platform or operating system. A system creates such a communication by defining the communication in markup language having a plurality of elements, adding canvas element(s) as one of the elements, inserting script within the markup language for defining the user specific and non-user specific content as a plurality of user specific and non-user specific objects, establishing coordinates for each of the user specific and non-user specific objects relative a defined origin, drawing each object at the coordinates established for the object in the canvas element(s) as canvas natives visible in the browser, and interpreting user initiated events for use in editing at least one of the plurality of user specific objects and the plurality of non-user specific objects.
US09501444B2
Disclosed are a USB device and a method thereof for automatically recognizing a Microsoft windowing operating system version. The method comprises: a USB device accessing a host; the USB device reporting an MOSD supporting a configuration parameter designation function to the host, a designation configuration value of the configuration parameter designation function being set to the Nth configuration parameter; when the USB device detects that the host obtains a configuration descriptor corresponding to the Nth configuration parameter, determining that a Windows operating system version is Win8; when the USB device detects that the host obtains a configuration descriptor corresponding to the first configuration parameter, and if the USB device receives only one query instruction delivered by the host, determining that a Windows operating system version is XP; or otherwise determining that the current Windows operating system version is Vista or Win 7. Embodiments of the present invention can distinguish Windows operating system versions without installing any program on a host.
US09501438B2
An information processing apparatus includes: a connection port configured to be capable of attaching a device thereto; an acquisition unit configured to acquire, from a storage unit included in the device, bus-configuration information indicating a bus configuration of the device; and a setting unit configured to set a bus configuration of the connection port based on the bus-configuration information.
US09501430B2
An X-ray imaging system comprises: an x-ray sensor including a wireless slave device and a first identification information communication unit that is associated with the wireless slave device; a wireless master device configured to wirelessly connect to the wireless slave device; a second identification information communication unit that is associated with the wireless master device and an x-ray tube that irradiates x-rays; and an identification information intermediating unit configured to receive and store identification information of the wireless slave device or on the wireless master device upon approaching one of the first and the second identification information communication units, and to transmit the identification information upon approaching the other one of the first and the second identification information communication units, wherein the wireless master device and the wireless slave device establish wireless connection based on the identification information.
US09501426B1
A system for dynamically utilizing data storage comprises a processor and a memory. The processor is configured to determine whether a data storage criterion is satisfied; and, in the event that the data storage criterion is satisfied: determine a new archiving threshold based on a target data storage usage level; and set the archiving threshold. The memory is coupled to the processor and is configured to provide the processor with instructions.
US09501423B2
A program execution device includes a program loader reading a machine language program including a machine language code and access frequency information; an address conversion table creator creating an address conversion table including entries, each of which indicates a relation between a logical address range and a physical address range; and a TLB register registering, in a TLB, an entry of the address conversion table storing a logical address range accessed according to the machine language code. When determining that the frequency of access to a logical address range is high based on the access frequency information, the address conversion table creator adjusts the size of an entry storing this logical address range to an appropriate size.
US09501398B2
A persistent storage device includes both persistent storage, which includes a set of persistent storage blocks, and NVRAM, and in particular a set of NVRAM blocks. The persistent storage device also typically includes a storage controller. The persistent storage device, in addition to responding to commands to write data directly to and to read data directly from persistent storage blocks is also configured to write data to specified NVRAM blocks (e.g., specified by a host NVRAM write command) and to transfer data from a specified NVRAM block to a specified persistent storage block. As a result, multiple writes to a particular persistent storage block can be replaced with multiple writes to an NVRAM block and a subsequent single write to the particular persistent storage block. This reduces the number of writes to persistent storage and also reduces the number of corresponding block erase operations.
US09501393B2
Managing data in a data storage system including at least one Data Storage Device (DSD) and a host. An initial location is determined for data to be stored in the at least one DSD based on at least one attribute defined by the host. A source portion is identified from a plurality of source portions in the at least one DSD for a garbage collection operation based on the at least one attribute defined by the host. A destination portion is identified in the at least one DSD for storing data resulting from the garbage collection operation based on the at least one attribute defined by the host. Garbage collection of the data in the source portion is performed into the destination portion, and after completion of garbage collection, the source portion is designated as a new destination portion for a new garbage collection operation.
US09501390B1
Disclosed are various embodiments for enhancing automated testing for mobile applications by using an automated testing set. An automated testing pattern set may include multiple patterns that have been determined to yield accurate results in testing applications within a particular application category. The automated testing pattern set may be created for each application category by applying automated random pattern generator tests to applications within the same application category and verifying the accuracy of the random patterns produced by the random pattern generator tests by comparing the results from manual testing. The automated testing pattern set is then created based on patterns ranked according to an assigned accuracy score.
US09501386B2
A computer system includes a processor and a data store coupled to the processor. An application component is operably coupled to the processor and the data store and is configured to run one or more applications stored in the data store. A test framework is coupled to the processor and the data store and is configured to perform at least one test relative to a component of the computer system that interacts with a database. A savepoint manager is configured to responsively generate at least one savepoint in the database prior to the at least one test and to roll back the at least one savepoint after the at least one test. Methods of testing the computer system are also provided.
US09501385B2
Various embodiments automatically test software automation scripts. In one embodiment, at least one software automation script is obtained. The software automation script is configured to automatically place a computing system into a target state. A plurality of test cases for the software automation script is executed. Each of the plurality of test cases is a separate instance of the software automation script configured based at least on one or more different states of the computing system. The software automation script is determined to be one of idempotent and non-idempotent and/or one of convergent and non-convergent based on executing the plurality of test cases.
US09501378B2
Embodiments for integrating production support features and recording client events are included in systems that initiate recording of the events occurring on a client application. The systems further receive event data transmitted from the client application, provide the event data on a display of a device of a user in real time, and allow the user to detect issues associated with the client application. The systems are combinable with additional production support features including module tracing.
US09501373B2
A data storage device includes memory devices including respective main regions and respective virtual regions, and a processor suitable for forming a super page by selecting main pages from the respective main regions, wherein when a main page of a main region in a memory device is a bad region, the processor forms a virtual super page by selecting a virtual page from a virtual region in the memory device instead of the main page.
US09501372B2
The present invention provides a cluster system that promptly stops access to a shared disk upon occurrence of abnormality. The cluster system is a cluster system where an active system server and a standby system server operate utilizing a shared disk. Each server includes: a disk input/output unit that accesses the shared disk by using data that is input and output via a predetermined bus; a fault detecting unit that, when a fault occurs in the active system server, detects the fault; and a bus closing unit that, when the fault detecting unit detects the fault, closes the bus by issuing an uncorrectable fault generation request to cause generation of an uncorrectable fault on the bus.
US09501369B1
Techniques to restore data from backup are disclosed. In various embodiments, an indication of a subcomponent to be restored from backup is received. View information associated with the backup is used to determine a set of physical components required to be retrieved from the backup to restore the requested subcomponent. The determined set of physical components is retrieved from the backup. The retrieved physical components are used to restore the subcomponent. In various embodiments, the view information includes data that identifies each of a plurality of separately-recoverable subcomponents of the backup and for each one or more physical components comprising the backup which would be required to restore that subcomponent.
US09501365B2
Cloud storage services can be used to facilitate secondary backup and disaster data recovery without the need for specialized backup servers at the secondary location or cloud storage service. Backup data streams are transferred to a cloud storage service. In addition to the backup data streams, backup metadata is generated for each backup data stream. The backup metadata is adapted to configure a backup server to retrieve and access data in the backup data stream. The backup metadata is also transferred to the cloud storage service. To access data from the backup data stream, a recovery backup system is connected with the cloud storage service. Backup metadata is transferred from the cloud storage service to the recovery backup system. The recovery backup system is updated with the backup metadata, which configures the recovery backup system to retrieve and access data in the backup data stream.
US09501359B2
Embodiments herein are directed to efficient crash recovery of persistent metadata managed by a volume layer of a storage input/output (I/O) stack executing on one or more nodes of a cluster. Volume metadata managed by the volume layer is organized as a multi-level dense tree, wherein each level of the dense tree includes volume metadata entries for storing the volume metadata. When a level of the dense tree is full, the volume metadata entries of the level are merged with the next lower level of the dense tree. During a merge operation, two sets of generation IDs may be used in accordance with a double buffer arrangement: a first generation ID for the append buffer that is full (i.e., a merge staging buffer) and a second, incremented generation ID for the append buffer that accepts new volume metadata entries. Upon completion of the merge operation, the lower level (e.g., level 1) to which the merge is directed is assigned the generation ID of the merge staging buffer.
US09501346B2
Systems, methods, and other embodiments associated with intelligently gathering log messages are described. In one embodiment, a computer-implemented method includes collecting, by a logging handler associated with a component, log messages according to two different granularities for logging messages. The two different granularities include a fine granularity and a coarse granularity. Collecting the log messages according to the fine granularity includes storing log messages in an incident buffer. The method includes, in response to detecting an error at the component, (i) freezing the incident buffer to preserve log messages present in the incident buffer, and (ii) communicating log messages that are collected according to the coarse granularity that are stored in a regular buffer to a logging appliance.
US09501342B2
System and method for construction, fault isolation, and recovery of cabling topology in a storage area network (SAN) is disclosed. In one embodiment, in a method for construction, fault isolation, and recovery of cabling topology in a SAN, subsystem information associated with each subsystem in the SAN is obtained. Then, an IP port and zoning information associated with connections of each subsystem is obtained. Component information associated with each component is also obtained. Any other relevant information associated with each subsystem and each component is obtained from users. The obtained subsystem information, IP port and zoning information, component information, and any other relevant information are compiled. Test packets are then sent from end-to-end in SAN using compiled information. The sent test packets are tracked via each component in each subsystem in the SAN. The cabling topology of the SAN is then outputted based on the outcome of the tracking.
US09501332B2
An apparatus include a first core processor, a second core processor, and a lock register coupled to the first core processor and to the second core processor. The apparatus further includes a shared structure responsive to the first core processor and to the second core processor. The shared structure is responsive to an unlock instruction issued by either the first core processor or the second core processor to send a signal to the lock register to reset a lock indication in the lock register.
US09501326B2
A load balancing system for performing stable processing and high reliability includes a management device which acquires time information indicating the time required in past processing on each of n processing devices, estimates a required time required for each processing devices to process processing target information based on the time information thereby obtaining an estimated time, and transmits estimated time information indicating a relationship between the estimated time and the processing device to a load balancing device. The load balancing device determines m (1
US09501322B2
Systems and methods for analyzing the service and performance levels associated with virtual machines in a storage network environment for compliance with a resource capacity policy are provided. Component configuration and connectivity information from components in the network environment is collected without using host agents on the virtual machines. Access paths defining end-to-end access relationships between an application on a virtual machine and storage data objects associated with the virtual machine in the network environment are derived. Access paths comprise sequences of components configured to enable information flow between an application residing on a virtual machine and a data object on a respective storage device. Access path resource consumption is computed and virtual machines with resource consumptions that violate the resource capacity policy are identified.
US09501321B1
Computing platforms may enable clients to use services to execute data processing tasks. Each of these services consumes resources during execution. Described herein are systems, devices and methods for generating resource consumption data for service calls. The resource consumption data may indicate amounts of resources consumed to process computational tasks associated with service calls. The system may determine when to process computational tasks based on the resource consumption data.
US09501319B2
Method, system, and computer-readable medium for scheduling blocking tasks are disclosed. A method includes: executing each of a plurality of task functions in a respective coroutine; detecting a first blocking event for a first task function of the plurality of task functions during execution of the first task function; in response to detecting the first blocking event: setting a respective blocking state of the first task function to a pause state; pausing execution of the first task function; and placing the first task function among a group of paused task functions; and after pausing the execution of the first task function: identifying a second task function among the group of paused task functions for which a respective blocking state has been updated to a running state; removing the second task function from the group of paused task functions; and resuming execution of the second task function.
US09501318B2
An apparatus for scheduling includes a receiving unit, configured to receive a task of a job; a configuration unit, configured to configure resource amounts for the task in at least two resource dimensions respectively, wherein each of the resource dimensions represents a resource available for configuring; and an interface unit, configured to distribute the task along with information about the resource amounts configured for the task in the resource dimensions.
US09501310B2
The execution of a process within a VM may be monitored, and when a trigger event occurs, additional monitoring is initiated, including storing behavior data describing the real-time events taking place inside the VM. This behavior data may then be compared to information about the expected behavior of that type of process in order to determine whether malware has compromised the VM.
US09501309B2
A method for configuring and maintaining external monitoring of one or more instances of a virtual machine within a virtualized computing environment. The method includes a computer processor monitoring a hypervisor. The method further includes a computer processor identifying a first list, wherein the first list is comprised of one or more monitoring templates respectively associated with one or more virtual machine types, and maintaining a second list comprised plurality of provisioned instances of virtual machines, wherein the second list also includes a first information respectively associated with the plurality of provisioned instances of virtual machines. The method further includes a computer processor compiling a third list and transmitting the third list to the monitoring system. The method further includes a computer processor receiving the third list and in response, a computer processor executing one or more monitoring functions based, at least in part, on the third list.
US09501307B2
Methods and systems for providing a communication path are disclosed. Information can be received via a first communication session based on a first messaging protocol. The first communication session can be terminated at a virtual machine of a group of virtual machines. A dynamically bound communication path to a resource can be selected based on a dynamically reconfigurable routing table for the group of virtual machines. A second communication session can be initiated, at the virtual machine, via the selected dynamically bound communication path. The information can be transmitted to the resource via the second communication session based on a second messaging protocol.
US09501304B1
An example method includes identifying a software package that is associated with a software application, wherein the software package includes platform-independent instructions that are configured to perform at least one computational task upon execution, and wherein the platform-independent instructions have a format that is not specific to any particular hardware platform. The method further includes selecting a computing system to perform the at least one computational task, providing, by the selected computing system, a container in which to perform the at least one computational task, obtaining, by the selected computing system, platform-dependent instructions that have been converted from the platform-independent instructions, wherein the platform-dependent instructions have a format that is specific to a hardware platform provided by the selected computing system, executing, by the selected computing system and in the container, the platform-dependent instructions to perform the at least one computational task.
US09501303B1
Systems and methods for managing computing resources are disclosed. In an example embodiment, a computing system request is received. The computing system request may be in a standardized request format and include a codified architecture and topology criterion. A build request is generated based on the computing system request. A computing resource device in accordance with the codified architecture and meeting the topology criterion is identified. A virtual machine is built on the computing resource device based on the build request. A plurality of applications is deployed on the virtual machine based on the build request to create an instantiated software deployment. Additional methods and systems are disclosed.
US09501295B2
Provided are a method, system, and computer program product for handling locale and language in a cloud management system, in which a first composite values list of applicable locales and matching languages combinations is generated from at least one language installed on a service management system and at least one locale supported by said service management system. A second composite values list of applicable locales and matching languages combinations is generated as a fall back list based on at least one base language of said service management system and at least one matching locale formed from said at least one base language, if said first composite values list of applicable locales and matching languages is empty. A resulting composite values list of valid locales and languages combinations is provided for further processing.
US09501293B2
Various embodiments of systems and methods for automatic context passing during management application navigation are described herein. When management applications work with different managed entities, the managed context is preserved by following the relations between the managed entities. These relations are followed from a mediator framework during the navigation between the management applications. In this manner, a managed application passes context information for one entity type, and second managed application retrieves from the framework context information for different entity type, but the user context information will be preserved as the framework follows the relations between the passed entity and the requested entity types.
US09501289B2
A computer system includes a memory storing an UEFI firmware and a processor. The UEFI firmware supports pre-boot initialization of a plurality of different bootloader programs, wherein the UEFI firmware has a plurality of instructions and a plurality of configuration data for different bootloader programs. The processor is operatively coupled to the memory and is used to execute the instructions of the UEFI firmware, wherein the instructions include performing the steps of: detecting type of instruction set of the processor; determining, by the processor, a bootup selection mode according to a mode selection, wherein the bootup selection mode corresponds to the detected type of instruction set, and the mode selection corresponds to the type of a bootloader program for execution after the UEFI firmware; retrieving, by the processor, a common configuration data from a plurality of configuration data of the UEFI firmware from the memory; retrieving, by the processor, a distinct configuration data from the plurality of configuration data of the UEFI firmware corresponding to the bootup selection mode from the memory, wherein the distinct configuration data comprises processor instruction sets and runtime services; generating a bootloader address corresponding to the bootup selection mode; and executing, according to the common configuration data and the distinct configuration data, the bootloader program located in a storage corresponding to the bootloader address.
US09501287B2
An embodiment provides an information handling device, including: a display panel and a base component connected by a hinge between the display panel and the base component, the hinge supporting a tent physical configuration and a stand physical configuration; one or more processors; an operating system; and instructions accessible to the one or more processors that when executed provide one or more actions comprising: determining via a first input regarding physical orientation of the information handling device that the operating system is to be operated in a first operational mode that is not supportive of the tent physical configuration or the stand physical configuration; operating the operating system in the first operational mode; and selectively altering a function of the first operational mode after receiving an additional input to support one or more of the tent physical configuration and the stand physical configuration. Other aspects are described and claimed.
US09501286B2
A superscalar pipelined microprocessor includes a register set defined by its instruction set architecture, a cache memory, execution units, and a load unit, coupled to the cache memory and distinct from the other execution units. The load unit comprises an ALU. The load unit receives an instruction that specifies a memory address of a source operand, an operation to be performed on the source operand to generate a result, and a destination register of the register set to which the result is to be stored. The load unit reads the source operand from the cache memory. The ALU performs the operation on the source operand to generate the result, rather than forwarding the source operand to any of the other execution units of the microprocessor to perform the operation on the source operand to generate the result. The load unit outputs the result for subsequent retirement to the destination register.
US09501283B2
Embodiments relate to cross-pipe serialization for a multi-pipeline computer processor. An aspect includes receiving, by a processor, the processor comprising a first pipeline, the first pipeline comprising a serialization pipeline, and a second pipeline, the second pipeline comprising a non-serialization pipeline, a request comprising a first subrequest for the first pipeline and a second subrequest for the second pipeline. Another aspect includes completing the first subrequest by the first pipeline. Another aspect includes, based on completing the first subrequest by the first pipeline, sending cross-pipe unlock signal from the first pipeline to the second pipeline. Yet another aspect includes, based on receiving the cross-pipe unlock signal by the second pipeline, completing the second subrequest by the second pipeline.
US09501267B2
A system and associated method for generating a Service Component Architecture (SCA) module with Service Oriented Architecture (SOA) model elements. A service model corresponds to a process model that has activities and a process flow. Services of the service model are respectively associated with the activities. Each service is determined to employ only one service operation definition to render a message specification of a respective activity that is associated with each service. The activities, the process flow, and the message specification are utilized to produce the SCA module in executable implementations.
US09501262B2
Embodiments relate to vectorized Galois field multiplication. An aspect includes an input of first and second input operands of equal sizes into a single hardware tree, a calculation of a predicted parity as a parity of the first input operand ANDed with a parity of the second input operand, a comparison of the predicted parity with a parity generated on a final result of a Galois field multiplication of the first and second operands and a raising of an error based on a mismatch between the predicted parity and the generated parity.
US09501258B2
A method of facilitating the reproduction of a presenter's desktop for attendees of a real-time collaboration. A bound portion of the desktop (the portion shared with the attendees) is logically divided into clusters. When the content of a cluster changes, the cluster is analyzed and one or more objects describing the content may be identified. Each object that is not already cached is cached and assigned a cache ID. Each object in the cluster is described in an object primitive to be sent to the attendees. Actions for reproducing the object on the attendees' clients are sent as action primitives. The object and action primitives allow the content of the presenter's desktop to be sent incrementally instead of sending the entire desktop.
US09501253B2
A communication apparatus (a printing apparatus 100) according to an aspect of the present invention controls communication with an external apparatus in one of a first wireless communication mode (or a wired communication mode) and a second wireless communication mode. In the case where the communication mode is set to the second wireless communication mode, the printing apparatus 100 switches the communication mode to the first wireless communication mode (or the wired communication mode) when an operation state of the printing apparatus 100 shifts to another state such as a power saving state.
US09501251B1
Techniques for print monitoring are disclosed. In one embodiment, the techniques may be realized as a method including monitoring a spool directory associated with a printing system; identifying, for a print job file, a file management call that is made before the print job file is submitted to a printer driver to carry out a print job; blocking the file management call; analyzing the print job file for sensitive data; in response to determining that the print job file does not include sensitive data, re-initiating the file management call for the print job file; and submitting the print job file to a printer driver to carry out a print job.
US09501248B2
An information processing apparatus includes a first controller, a second controller, a non-volatile storage medium, and a volatile storage medium. The non-volatile storage medium is able to store data under control by the first controller, and unable to store data under control by the second controller. The volatile storage medium is able to store data under control by the second controller such that the data are readable therefrom under control by the first controller. The second controller includes a first storage unit that stores history data of operation performed under control by the second controller in the volatile storage medium. The first controller includes a reading unit and a second storage unit. The reading unit reads the history data stored in the volatile storage medium by the first storage unit. The second storage unit stores the history data read by the reading unit in the non-volatile storage medium.
US09501245B2
A new approach is proposed that contemplates systems and methods to virtualize a physical NVMe controller associated with a computing device or host so that every virtual machine running on the host can have its own dedicated virtual NVMe controller. First, a plurality of virtual NVMe controllers are created on a single physical NVMe controller, which is associated with one or more storage devices. Once created, the plurality of virtual NVMe controllers are provided to VMs running on the host in place of the single physical NVMe controller attached to the host, and each of the virtual NVMe controllers organizes the storage units to be accessed by its corresponding VM as a logical volume. As a result, each of the VMs running on the host has its own namespace(s) and can access its storage devices directly through its own virtual NVMe controller.
US09501241B2
A storage system comprises a second NAS storage apparatus comprising a processor and a storage medium and a third NAS storage apparatus for migrating an object managed by a first NAS storage apparatus. The processor stores path information of an object for which migration has started after including the path information in object management information, in the storage medium prior to migrating the object entity to the third NAS storage apparatus. The processor, after receiving the object entity from the first NAS storage apparatus and migrating the object entity to the third NAS storage apparatus, stores the third NAS storage apparatus path information to the object entity in the object management information, and reflects the management information in the third NAS storage apparatus.
US09501239B2
The present invention relates to a grouping method and device for enhancing redundancy removing performance for a storage unit such as a hard disk, a solid state disk (SSD), etc. The grouping method for enhancing performance of a redundancy removing technology may include: extracting samples from data that is stored in a buffer of a memory and is standing by to be processed; performing remaining calculations on the extracted samples; and grouping samples by connecting them to a bucket corresponding to a resultant value of the remaining calculations.
US09501232B2
Execution of a transaction mode setting instruction causes a computer processor to be in an atomic write-only mode ignoring conflicts to certain read-sets of a transaction during transactional execution. Write-set conflicts may still cause a transactional abort. Absent any aborting, the transaction's execution may complete, by committing transactional stores to memory and updating architecture states.
US09501231B2
A storage system is provided with a memory region, a cache memory region, and a processor. The memory region stores the time relation information that indicates a time relationship of a data element that has been stored into the cache memory region and that is to be written to the logical region and a snapshot acquisition point of time to the primary volume. The processor judges whether or not the data element that has been stored into the cache memory region is a snapshot configuration element based on the time relation information for the data element that is to be written to a logical region of a write destination that conforms to the write request that specifies the primary volume and that has been stored into the cache memory region. In the case in which the result of the judgment is positive, the processor saves the data element to the secondary volume for holding a snapshot image in which the snapshot configuration element is a configuration element, and a data element of a write target is then stored into the cache memory region.
US09501229B1
Techniques are provided for multi-tiered coarray programming. An exemplary coarray programming method comprises obtaining an index address identifying a memory element in a memory array in a multi-tiered storage environment, wherein the index address comprises an identifier of a storage tier within the multi-tiered storage environment where the memory element is stored; and converting the index address to one or more of a path name, an object name and a key value based on the identified storage tier to access the memory element. Exemplary aspects of the invention extend a coarray programming model to employ one or more of a file interface and an object interface for remote storage tiers.
US09501227B2
A memory controller for heterogeneous computer processors dynamically adjusts access priorities by the different processors to maximize performance in the execution of a single parallel application program on both processor architectures. In one embodiment, the memory controller predicts sequential memory accesses by the processor having higher memory latency or fewer access requests to lockout the other processor during those sequences for improved implementation of the intended prioritization.
US09501221B2
According to one embodiment, a method for dynamically changing a buffer threshold in a tape drive includes determining that a drive buffer is emptied of data, calculating a write size indicating an amount of data from a transaction size left to be written to a tape prior to a next anticipated sync command, setting a buffer threshold that triggers a back hitch to a smaller value when the transaction size is less than a buffer size, setting the buffer threshold to the smaller value when an absolute difference between the transaction size and the write size is greater than or equal to the buffer size, and setting the buffer threshold to a larger value when the transaction size is not less than the buffer size and/or the absolute difference between the transaction size and the write size is less than the buffer size.
US09501220B2
An information processing apparatus that detects touch input at a touch panel disposed on or formed integrally with a display, extracts one or more character strings from a plurality of character strings displayed on the display based on the detected touch input, prioritizes the extracted one or more character strings, and controls the display to display the extracted one or more character strings in order based on the prioritizing.
US09501214B2
A mobile terminal including a memory configured to store data; a touchscreen display; and a controller configured to: display a first portion of a panoramic file selected from the memory, said panoramic file having a display size greater than that of the touchscreen display, and scroll automatically the panoramic file in at least one direction so as to display another portion of the panoramic file.
US09501213B2
A method for scheduling an event in a calendar application is disclosed wherein the event is held at a fixed position on the screen of a device and a calendar grid is dragged relative to the event. The method is well-suited for touch devices and provides a way for the user to easily create and schedule events directly on a calendar grid without the need to enter event start and end times into a form. A view finder assists the user to set the desired start and end time. The view finder supports different zoom precisions which allow the user to enter start and end times of any granularity such as one minute granularity. A micro-dragging technique provides a way to easily select start and end times with high precision. The method may be extended to general applications where it is desirable to drag objects on a workspace.
US09501210B2
An information processing apparatus includes a display device configured to display a first image, a coordinate input device configured to input coordinates on the first image, and a processor configured to perform processing based on input to the coordinate input device. The processor specifies a part of a region on the first image as a specific region, based on coordinates of two points that are input to the coordinate input device, generates a second image that is obtained by enlarging the specific region at a predetermined magnification, and causes the display device to superimpose and display the second image on the first image with the second image occupying a part of the first image.
US09501209B2
A National Online Parcel-Level Map Data Portal (NPDP) is provided that optimizes online delivery of parcel-level maps and linked attribute data. To do this, the NPDP manages a database of assembled and current vector based parcel data in a spatial format (GIS) that enables geocoded parcel boundaries to be linked to property tax records. A user enters a street address into an appropriate screen window to call up and view road right-of-ways, all parcel boundaries and the “exact” address location as a highlighted parcel area. In addition, a list of property record attributes such as owner, use code, assessed value and year constructed can be displayed. Other on screen parcels can likewise be selected if one wishes to view their linked attributes.
US09501205B2
A system is described for providing a virtual environment corresponding to a scene from nature. The virtual environment can be used to present performance metrics to a user. In some examples, the virtual environment can be a pond where performance metrics are represented using lily pads. The visual appearance of the lily pad can be dependent on metadata of the corresponding performance metric and the lily pads can be grouped according to how the performance metrics are grouped in the database.
US09501202B2
Methods and computer apparatuses are disclosed for processing genomic data in at least partially automated workflows of modules. A method comprises: specifying a source from which nucleic acid sequence(s) are to be obtained; selecting module(s) for processing data, including at least one module for processing the one or more nucleic acid sequences; presenting, in a graphical user interface, graphical components representing the source and the module(s) as nodes within a workspace; receiving, via the graphical user interface, inputs arranging the source and the module(s) as a workflow comprising a series of nodes, the series indicating, for each particular module, that output from one of the source or another particular module is to be input into the particular module; generating an output for the workflow based upon the nucleic acid sequence(s) by processing each module in an order indicated by the series.
US09501198B2
A touch panel includes: a first resistance film; a second resistance film spaced apart from the first resistance film; a first electrode and a second electrode that are provided on the first resistance film, and are opposite to each other in a first direction; a third electrode and a fourth electrode that are provided on the second resistance film, and are opposite to each other in a second direction; an application unit that applies voltages to the first to the fourth electrodes, respectively; and a coordinate detection unit that, when the first resistance film comes in contact with the second resistance film at two points, detects coordinates of the two points based on a voltage applied between the first and the second electrodes, a voltage applied between the third and the fourth electrodes, and a voltage caused by a contact resistance between the first and the second resistance films.
US09501186B2
A touch screen, including: at least two cover glasses; a flexible film; a coating layer coating the flexible film; a transparent bonding layer bonding the flexible film that is coated with the coating layer to the at least two cover glasses; and a flexible printed circuit board electrically connected to the coating layer.
US09501176B1
A method, apparatus, and manufacture for writing and annotation is provided. An image is provided on a surface. In one embodiment, each time invisible ink is deposited on the surface, the location of the invisible ink deposited on the surface is detected before the invisible ink vanishes from the surface. In another embodiment, when a tip of a stylus is in contact with a location of an image on the surface, employing three or more light detectors to detect light at the location. The detected light is employed to determine a position and an orientation of the tip of the stylus and the location on the surface, and modifying the image based on the stored information.
US09501174B2
Systems, methods, and computer-readable media for determining the temperature of a light-generating component of a display assembly using a voltage of the light-generating component are provided. In one embodiment, a method for operating an electronic device, which may include an external surface and a light-emitting diode operative to emit light for illuminating the external surface, may include detecting the forward voltage of the light-emitting diode, calculating the temperature of the light-emitting diode using the detected forward voltage of the light-emitting diode, and altering the performance of the electronic device based on the calculated temperature of the light-emitting diode. Additional embodiments are also provided.
US09501170B2
The present invention is directed to a pixel circuit for a display device and to a method for driving the pixel circuit. The pixel circuit comprises: a light-emitting unit configured to emit light under the control of the light-emission controlling unit; a light-emission controlling unit configured to control the light-emitting unit to emit light at a display stage; a touching unit configured to generate a touch signal; a driver amplifying unit configured to amplify the touch signal at a touch stage and drive the light-emitting unit to emit light at the display stage; a charging unit configured to charge a compensating unit; the compensating unit configured to be charged by the high voltage end prior to the display stage, and be charged by the charging unit at the display stage.
US09501162B2
A display device integrated with a touch screen panel includes a display unit in which scan lines and data lines crossing each other, and pixels are arranged, wherein the pixels are positioned at crossing regions of the scan lines and the data lines and each of the pixels comprises first and second pixel electrodes, first touch electrodes extending along a first direction on the display unit, and second touch electrodes extending along a second direction on the display unit, and arranged to overlap the first touch electrodes, the second touch electrodes being spaced apart from the first touch electrodes, wherein the first touch electrodes are implemented by patterning the second pixel electrode in the first direction, and wherein while a touch driving signal is supplied to one or more first touch electrodes among the first touch electrodes, a second pixel power source is supplied to remaining first touch electrodes.
US09501155B2
In embodiments of portable device pairing with a tracking system, a pairing system includes a portable device that generates device acceleration gesture data responsive to a series of motion gestures of the portable device. The pairing system also includes a tracking system that is configured for pairing with the portable device. The tracking system recognizes the series of motion gestures of the portable device and generates tracked object position gesture data. A pairing service can then determine that the series of motion gestures of the portable device corresponds to the series of motion gestures recognized by the tracking system, and communicate a pairing match notification to both the tracking system and the portable device to establish the pairing.
US09501148B2
A portable display device includes: an acceleration sensor; an outputting section outputting a detection signal when a measurement value changes across a reference value; a calculating section calculating a duration time in which the measurement value exceeds the reference value; a judging section judging whether the movement state is due to running based on an occurrence frequency of the movement state and the duration time; a setting section setting a running state when the movement state is due to the running; a calculating section calculating a time interval between the movement states; a continuous tap judging section judging whether the movement states are due to continuous tap operations according to a judgment condition based on the duration time and time interval; and a setting range changing section setting a range of the judgment condition in the running state to be broader than that in a non-running state.
US09501145B2
An apparatus that includes a conductive surface and an insulation surface disposed on the conductive surface. The apparatus further includes a controller configured to cause a signal to be coupled to the conductive surface such that a tactile sensation is perceived in a digit that slides on the insulation surface.
US09501136B2
A highly convenient information processing device is provided. The information processing device according to the present disclosure includes a communication unit, a storage unit in which an OS and a program are stored, and a processor configured to execute a predetermined program based on identification information of a predetermined network when the communication unit establishes a connection to the predetermined network. In a case where the communication unit establishes a connection to the predetermined network when the information processing device is in a sleep state, the processor does not execute the predetermined program, and after the sleep state is cleared, the processor executes the predetermined program.
US09501130B2
A data processing system includes a host device including a first volatile memory device, and a data storage device including a second volatile memory device and a nonvolatile memory device, and suitable for storing data to be accessed by the host device. The data storage device uploads data stored in the second volatile memory device to the first volatile memory device before the data storage device in a normal mode enters a power-save mode.
US09501128B2
Method of cooperative reduced power mode suspension for high input/output (‘I/O’) workloads, including: determining, by a transfer monitoring module, a size of a file to be transferred to a recipient, wherein the recipient includes a central processing unit (‘CPU’) operating in a reduced power mode; determining, by the transfer monitoring module, a desired transfer rate for transferring the file to the recipient; calculating, by the transfer monitoring module, an expected transfer completion time in dependence upon the size of the file and the desired transfer rate; and sending, by the transfer monitoring module, a message to the recipient requesting that the CPU suspend the reduced power mode in dependence upon the expected transfer completion time.
US09501111B1
A fan assembly includes a housing including two first slits on a bottom; a mount on the housing and including two second slits aligned with the first slits; a louver on the housing and including openings and at least one outtake between the louver and a front of the housing; first and second side caps for fastening the housing and the louver together; a PCB on a side of the housing; an exposed touch screen adjacent to the PCB and configured to activate the PCB; a transverse fan in the mount and electrically connected to the PCB; two pivotal members each including two opposite projections slidably disposed in the first and second slits; and two auxiliary supports on the at least one outtake, each auxiliary support including a shaft rotatably disposed in the pivotal member, and slots.
US09501099B2
An electronic device is provided. The electronic device can include one or more protrusions and a casing. The casing can be shaped and dimensioned to carry the audio output portions. The casing can include a first face, a second face and sides. The one or more protrusions can extend from any of, or any combination of, the first face, the second face and at least one of the sides.
US09501086B2
A phase coherent signal generator apparatus is disclosed that outputs a coherent continuous phase signal that includes fast switched multiple different frequency bursts. The apparatus comprises: a clock generator including an input to receive a reference clock signal, and outputs to independently supply a master clock signal and a slave clock signal; an accumulating digital synthesizer that includes independent inputs to receive the slave clock signal, a digital frequency tune word signal, a phase tune word signal, and a reset signal, and an output that supplies a digital coherent continuous phase signal; a master digital synthesizer that includes independent inputs to receive the master clock signal and the digital frequency tune word signal, and independent outputs to supply the digital phase tune word signal and the reset signal; and a converter that receives the digital coherent continuous phase signal and supplies the coherent continuous phase signal.
US09501083B2
An accelerator and brake pedal device includes a connecting lever, a brake pedal assembly, an accelerator pedal assembly, an accelerator control circuit, and a resisting member. The brake pedal assembly is coupled to the connecting lever. The accelerator pedal assembly is rotatably coupled to the brake pedal assembly. The accelerator control circuit has an accelerator control switch. The resisting member is positioned on the connecting lever away from the brake pedal assembly. The accelerator control switch is resisted to turn off by the resisting member and break the accelerator control circuit. The resisting member is moved by the accelerator pedal assembly toward the accelerator control switch. The accelerator control circuit is rendered inoperative when the resisting member is moved by the accelerator pedal assembly toward the accelerator control switch. The accelerator control circuit is rendered operative when the accelerator pedal assembly is released.
US09501082B2
A dampener assembly for a lever is provided. The dampener assembly includes a travel limiter that defines a surface for co-acting with the dampener. The lever is configured to move from a locked position to an unlocked position to unlock a component for adjustable movement. The dampener assembly includes also a roller bumper and cam assembly that is configured to cause the surface of the travel limiter to contact the roller bumper in the unlocked position. In an exemplary embodiment, the component is a rake-telescope steering column or an adjustment assembly therefor.
US09501067B2
A system actively regulates the fluid pressure entering the pump of a fluid-dispensing system to provide a more uniform fluid flow exiting the pump. The pump is supplied with fluid from a pressurized reservoir (e.g., that is pressurized from an external air source, or by mechanical or electrically-driven pressurization). A pressure sensor monitors the fluid pressure in the fluid supply line between the reservoir and pump. A controller receives this fluid pressure reading as an input to regulate the pressurization of the reservoir. Optionally, a second pressure sensor can be used to monitor the fluid pressure at the pump exit to provide an additional input for the controller.
US09501058B1
A vehicle has a plurality of control apparatuses, a user input, a geographic position component, an object detection apparatus, memory, and a display. A processor is also included and is programmed to receive the destination information, identify a route, and determine the current geographic location of the vehicle. The processor is also programmed to identify an object and object type based on object information received from the object detection apparatus and to determine at least one warning characteristic of the identified object based on at least one of: the object type, a detected proximity of the detected object to the vehicle, the location of the detected object relative to predetermined peripheral areas of the vehicle, the current geographic location of the vehicle, and the route. The processor is also configured to select and display on the display an object warning image based on the at least one warning characteristic.
US09501056B2
A robotic device includes a housing configured to house a mobile device. The robotic device also includes an articulating image director aligned with a field of view of a camera of the mobile device. The housing of the robotic device is positioned at an angle to provide a forward view or rear facing view to the camera via the articulating image director.
US09501051B2
An exemplary aspect comprises a control apparatus comprising: (a) a controller comprising a microprocessor; (b) a wireless transceiver in communication with said microprocessor and operable to communicate over a wireless network with an application on a mobile device; (c) a light switch controlled by the controller; (d) a sensor in communication with the controller; and (e) a front panel that allows a user to interface with the controller.
US09501045B2
A radio wave receiver, that receives satellite waves, includes a GPS reception processing unit configured to receive signals from a plurality of positioning satellites, acquire data necessary for positioning from the received signals, calculate a current location of the radio wave receiver, save a failure history related to acquisition of the data necessary for positioning with respect to each of the received signals, determine a reception condition of each of the received signals in accordance with the failure history, and suspend acquisition of the data necessary for positioning with respect to a signal having the reception condition determined to be at least equal to a predetermined reference level, the signal being among the signals from the plurality of positioning satellites.
US09501037B2
A timepiece case band including a peripheral shoulder in which an annular rotating bezel system is rotatably mounted. The rotating bezel system is an independent module including an annular bezel, an annular support element, a toothed element, and a spring mechanism cooperating elastically with a snap-fit mechanism, the spring mechanism and the toothed element being axially retained by the bezel and/or the support element. The rotating bezel system further includes a securing mechanism securing the spring mechanism, support element, and bezel to each other.
US09501021B2
A sheet processing apparatus includes a binding unit configured to perform binding processing by pressing a sheet bundle, a motor configured to drive the binding unit to press the sheet bundle, a speed detection unit configured to detect a speed of the motor, a voltage detection unit configured to detect a driving voltage of the motor, and a motor control unit configured to determine an upper limit value of a driving current of the motor based on the speed detected by the speed detection unit and the driving voltage detected by the voltage detection unit in a period when the motor is being driven and the binding unit is not pressing the sheet bundle.
US09501012B2
A fixing apparatus for fixing a toner image to a recording material includes a cylindrical film, a heater configured to make contact with the film, the heater including a substrate and a heat generation resistor formed on the substrate, and a heat conduction member configured to make contact with a surface of the heater opposite to a surface thereof being in contact with the film, the heat conduction member having a higher thermal conductivity than that of the substrate, and being divided into parts in a generatrix direction of the film. The toner image formed on the recording material is fixed on the recording material by using heat of the film, and one of the parts of the heat conduction member is configured to make contact with the heater continuously from a center to an end of a heat generation region of the heater in the generatrix direction.
US09501009B2
A fixing device according to the present invention includes a fixing belt (21), a cap member (28) attached to an end part (21a) of the fixing belt (21) and an elastic member (29) arranged between the fixing belt (21) and the cap member (28). The cap member (28) includes a main body part (55) covering an outside of the end part (21a) of the fixing belt (21) and a flange part (56) extending from the main body part (55) to an inside and covering an outer diameter side of the end part (21a) of the fixing belt (21). A step (s) is formed in an inner circumference face of the flange part (56). An outer circumference face of the elastic member (29) comes into contact with an inside part from the step (s) in the inner circumference face of the flange part (56).
US09501005B2
A fixing device includes a roller, a plurality of heaters, a temperature detection unit, and a control unit, wherein when the temperature detection unit detects that the temperature of longitudinal end portions of the roller is lower than a preset reference temperature, the control unit performs full-lighting control on the heater with the largest amount of heat supply to the end portions of the roller, out of the plurality of heaters, and performs lighting control on the heater with the second largest amount of heat supply to the end portions of the roller in a pattern at a predetermined duty ratio, or performs lighting control on the heater with the largest amount of heat supply to the end portions of the roller in a pattern at a predetermined duty ratio, and turns off the heater with the second largest amount of heat supply to the end portions of the roller.
US09501002B2
An endless belt exchangeably usable with an image forming apparatus, the endless belt including a first lubrication layer applied on an inner surface of the endless belt, the first lubrication layer including lubrication particles and lubricant oil; a second lubrication layer provided on the first lubrication layer and including lubrication particles and lubricant oil; wherein a lubricant oil content of the first lubrication layer is larger than a lubricant oil content of the second lubrication layer.
US09500991B2
A developing apparatus, includes a developer carrying member; a containing portion configured to contain developer; a discharge outlet through which a surplus of the developer is discharged; a first conveying portion configured to convey the developer; a second conveying portion provided downstream of the first conveying portion in a conveying direction of the first conveying portion and having a spiral blade portion configured to convey the developer in a conveying direction opposite to the conveying direction of the first conveying portion; and a disk portion provided upstream of the second conveying portion in the conveying direction of the second conveying portion, the disk portion being formed to project radially-outwardly from a whole circumference of a rotary shaft. An upstream end of the spiral blade portion of the second conveying portion in the conveying direction of the second conveying portion and the disk portion are arranged with an interval therebetween.
US09500983B2
An image forming apparatus includes an image bearer, a developing device to develop with developer a latent image formed on the image bearer, a developer container to contain developer, a temporary reservoir to temporarily store developer supplied from the developer container and having an outlet to discharge the temporarily stored developer to the developing device, a first conveyance device to transport developer from the developer container to the temporary reservoir, a second conveyance device to transport developer from the temporary reservoir to the developing device, a first developer amount detector to detect an amount of developer in the temporary reservoir, and a controller to control driving of the first conveyance device based on a detection result generated by the first developer amount detector and data relating to driving of the second conveyance device.
US09500980B2
An image forming apparatus capable of controlling an amount of light beam to be a target value even when an emission characteristic of a light source varies. A photosensitive member is exposed to the light beam emitted form a light source. A light receiving element receives the light beam. Voltage for prescribing the driving current is set in a voltage setting unit. A voltage control unit controls the voltage so that the light amount of the light beam received by the light receiving element becomes a target light amount. A determination unit determines a correction parameter for correcting the voltage based on at least the voltage set in the voltage setting unit. A correction unit corrects the voltage set in the voltage setting unit with the correction parameter. A current supply unit supplies a driving current corresponding to the corrected voltage to the light source based on image data.
US09500979B2
In a configuration in which a charging roller contact unit of a contact unit is located in a periphery of a mounting surface for mounting a cleaning blade of a drum cartridge frame, at least a part of the charging roller contact unit of the contact unit is formed in such a manner that an area of a cross section perpendicular to a direction approaching to the mounting surface of the cleaning blade becomes smaller with an approach to the mounting surface of the cleaning blade.
US09500978B2
An image forming apparatus includes a first electric charging unit having an electric discharge wire to uniformly electrify a surface of the electrostatic latent image bearer, a second electric charging unit having a second electric discharge wire to execute a pre-electric charge removal electric charging process by electrifying the surface of the electrostatic latent image bearer subsequent to a transfer process to transfer a toner image, and a first electric charge removing device to diselectrify the surface of the electrostatic latent image bearer by irradiating it with electric charge removing light subsequent to the pre-electric charge removal electric charging process. The first electric charge removing device is disposed within an electric discharge region of the second electric discharge wire on a downstream side of an extreme upstream edge of the electric discharge region of the second electric discharge wire in a rotational direction of the electrostatic latent image bearer.
US09500974B2
A toner includes a plurality of toner particles each including a core and a shell layer disposed over a surface of the core. The shell layers include a resin containing a unit derived from a thermoplastic resin and a unit derived from a monomer or prepolymer of a thermosetting resin. The toner has an average roundness of no less than 0.965 and no greater than 0.975. The toner contains less than 0.5% by number of toner particles having a roundness of no greater than 0.85. The toner has a displacement rate of no less than 0.50% and no greater than 0.70% as measured in a micro-compression test that is performed on the toner under specified conditions.
US09500973B2
For at least 80% of toner particles in a toner, along at least 80% of circumferential length of a toner particle cross-section, a shell layer has a thickness of at least 5 nm and satisfies a condition that a ratio of an intensity INc relative to an intensity INs is no greater than 0.2. For at least 80% of the toner particles in the toner, along at least 80% of the circumferential length of the toner particle cross-section, the shell layer has a thickness of at least 5 nm and satisfies a condition that a ratio of an intensity ISc relative to an intensity ISs is no greater than 0.2.
US09500967B2
An undercoat layer of an electrophotographic photosensitive member includes a product having electron transportability and a particle including titanium oxide, and a surface layer of the electrophotographic photosensitive member includes a product of a composition including a hole transporting substance having a polymerizable functional group and a photopolymerization initiator.
US09500961B2
According to one embodiment, According to one embodiment, a pattern formation method includes disposing a mask and a substrate separately from each other, the mask having a plurality of light transmitting portions arranged periodically. The method includes irradiating the mask with illumination light emitted from an optical part to irradiate the substrate with at least a part of the illumination light transmitted through the light transmitting portions. a distance d between the mask and the substrate, a wavelength λ of the illumination light, a pitch p of an arrangement of the light transmitting parts, a numerical aperture NAi of the optical part, and at least one natural number n satisfy the following. p≧2λ, (np2/λ)−α≦d≦(np2/λ)+α, α=p2(2λ) and λ/(8np)≦NAi<λ/(2np).
US09500956B2
The disclosure relates to optical systems of a microlithographic projection exposure apparatus, and to a microlithographic exposure method. According to an aspect of the disclosure, an optical system has a light source, a ray-splitting optical element, which splits a light ray incident on this element when the projection exposure apparatus is in operation into a first partial ray and a second partial ray, with the first and the second partial ray having mutually orthogonal polarization directions, and at least one ray-deflecting optical element for generating a desired polarized illumination setting from the first partial ray and the second partial ray, wherein the ray-splitting optical element is arranged such that light incident on this ray-splitting optical element when the projection exposure apparatus is in operation has a degree of polarization of less than one.
US09500955B2
An exposure apparatus comprises a light source (1) and a diffusing sheet (2) provided below the light source (1), a side of the diffusing sheet (2) adjacent to the light source (1) is an incident face (21) and the other side opposite to the incident face (21) is an emitting face (22); the light emitted from the light source (1) enters the diffusing sheet (2) through the incident face (21), is refracted within the diffusing sheet (2), and after being diffused, emits out evenly throughout the emitting face (22). The exposure apparatus enables an evenly exposure of the photoresist on the substrate. An exposure method using such an exposure apparatus is also disclosed.
US09500952B2
An orthogonal process for photolithographic patterning organic structures is disclosed. The disclosed process utilizes fluorinated solvents or supercritical CO2 as the solvent so that the performance of the organic conductors and semiconductors would not be adversely affected by other aggressive solvent. One disclosed method may also utilize a fluorinated photoresist together with the HFE solvent, but other fluorinated solvents can be used. In one embodiment, the fluorinated photoresist is a resorcinarene, but various fluorinated polymer photoresists and fluorinated molecular glass photoresists can be used as well. For example, a copolymer perfluorodecyl methacrylate (FDMA) and 2-nitrobenzyl methacrylate (NBMA) is a suitable orthogonal fluorinated photoresist for use with fluorinated solvents and supercritical carbon dioxide in a photolithography process. The combination of the fluorinated photoresist and the fluorinated solvent provides a robust, orthogonal process that is yet to be achieved by methods or devices known in the art.
US09500951B2
There is provided an actinic ray-sensitive or radiation-sensitive resin composition containing a resin (P) having a repeating unit represented by the following Formula (A) and having at least two of a repeating unit represented by the following Formula (B), a repeating unit represented by the following Formula (C), a repeating unit represented by the following Formula (D) and a repeating unit represented by the following Formula (E).
US09500937B2
A light source device includes a light source, a first dichroic mirror, and a light emitting member. The light source is configured to emit blue light substantially polarized in a first direction. The first dichroic mirror is configured to reflect not less than 80% and not more than 90% of the blue light polarized in the first direction, and to transmit more than 10% and less than 20% of the blue light polarized in the first direction, in a wavelength band of blue light. The light emitting member is configured to emit light upon being excited by the blue light reflected by the first dichroic mirror.
US09500933B2
A system, method, and apparatus for delayed optical logic gates based on slow light and enhanced nondegenerate four-wave mixing processes, where a single or multiple delayed optical routers are utilized for dark resonance interactions in which two-color lasers interact with a three-level nonlinear optical medium comprised of two ground states and one excited state through the nondegenerate four-wave mixing processes. The delayed optical logic mechanism is based on combination of single or multiple dark resonance-induced two-photon coherence conversion via slow light phenomenon. The two-photon coherence induced on the ground states is optically detected via nondegenerate four-wave mixing processes. The nondegenerate four-wave mixing generation is enhanced owing to dark resonance or electromagnetically induced transparency. The delayed optical logic gates have potential to keep up ultra-high-bandwidth optical information processing using relatively slow electronic processing devices.
US09500929B2
An electro-optically coupled switch includes first and second waveguides which are aligned in parallel to each other, with a thin, flat layer of cross-coupling material sandwiched therebetween. A voltage source is provided to establish a strong uniform electric field that is oriented perpendicular across the entire layer of cross-coupling material between the waveguides. Incorporated with the voltage source is a switch for changing the electric field, to thereby alter the refractive index of the cross-coupling material for transferring the transmission of an optical signal from one waveguide to the other.
US09500927B2
An electrochromic device including a first substantially transparent substrate having an electrically conductive material associated therewith; a second substrate having an electrically conductive material associated therewith; and an electrochromic medium contained within a chamber positioned between the first and second substrates which includes: at least one solvent; at least one anodic electroactive material; at least one cathodic electroactive material; wherein at least one of the anodic and cathodic electroactive materials is electrochromic; and a creep resistant crosslinked polyelectrolyte gel matrix.
US09500922B2
An array substrate, a LCD panel and a display device are disclosed. The array substrate includes: a substrate, a plurality of pixels disposed on the substrate and defined by a plurality of gate lines and a plurality of data lines. A common electrode and a pixel electrode are disposed in each pixel region. Two pixels at adjacent rows in a same column form a pixel set. A first gate line and a second gate line are disposed between the two pixels of the pixel set. The data line is disposed on the same side of the two pixels. A first switch transistor and a third switch transistor are disposed in one pixel region of the pixel set and at least a second switch transistor is disposed in the other pixel region.
US09500920B2
The present invention discloses a liquid crystal display (LCD) panel and method for forming the same. In the LCD panel, the TFT includes a source and a drain formed by a transparent conducting layer, and a gate formed by a metal layer. The source is electrically connected with a data line through a via hole over the data line. The source connects to the drain via an active layer. Whatever the number of data lines are, each pixel corresponds to an associated via hole, so the number of via holes does not increase, and not reduce the aperture ratio. Therefore, the present invention is very proper to a design using more data lines and working in a high frequency. Moreover, the matrix circuitry of LCD of the present invention is well applied in a display which not only increases a density of data lines to raise the frame rate, but also maintains the aperture ratio and brightness.
US09500910B2
At a corner of a TFT substrate where sealants are coated overlapping each other, a phenomenon that the sealants protrude into the display region is prevented by a structure that: the TFT substrate having an organic passivation film is formed as far as the outside of the display region. A groove-like organic passivation film removed portion is formed surrounding the display region. Since the sealants are coated overlapping each other at the corner, when a TFT substrate and a counter substrate are superposed at a predetermined gap, the width of the groove-like organic passivation film removed potion is made larger at the corner than the side in order to prevent the sealant from extending. Since an excessive sealant is absorbed in the groove-like organic passivation film removing portion of a larger width at the corner, the sealant can be prevented from protruding to the inside of the display region.
US09500906B2
A display apparatus including a screen layer for displaying a unified image to a viewer and an illumination layer having an array of light sources. Each light source emits a light beam. An array of optical elements, each coupled to a corresponding light source in the array of light sources, is disposed between the screen layer and the illumination layer. The display layer includes a matrix of pixlets and a spacing region disposed between the pixlets in the matrix, wherein the array of light sources emit their light beams through the array of optical elements, wherein each optical element is configured to shape the received light beam into a divergent projection beam having a limited angular spread to project sub-images displayed by the pixlets as magnified sub-images on the backside of the screen layer, the magnified sub-images to combine to form the unified image that is substantially seamless.
US09500905B2
A liquid crystal display device including: a liquid crystal panel 2; a diffuser 3 provided behind the liquid crystal panel 2; a light guide member 4 provided behind the diffuser 3; and a case supporting the liquid crystal panel 2, the diffuser 3, and the light guide member 4, where the case includes an opening at the back, the light guide member 4 is provided covering the opening, and the light guide member 4 includes a first prism 7 including an incident surface 8 on which outside light from above is incident, and a first slope surface 9 provided below the incident surface 8, and reflecting light incident from the incident surface 8 and on which outside light from behind is incident, the liquid crystal display device being able to make use of outside light efficiently.
US09500901B2
A liquid crystal display includes a first polarizer and a liquid crystal display panel adhered to the first polarizer. The first polarizer includes a first sub-areas and a first center area. An adhesion intensity of the first polarizer and the liquid crystal cell corresponding to the first sub-area is greater than an adhesion intensity of the first polarizer and the liquid crystal cell corresponding to the first center area.
US09500899B2
A transistor substrate may include a transistor. The transistor substrate may further include a set of color filters that has at least two different colors, overlaps the transistor, and defines a hole. The hole exposes a portion of the transistor.
US09500883B2
A spectacle lens is disclosed. The disclosed lens provides a vision correcting area for the correction of a wearer's refractive error. The viewing correction area provides correction for non-conventional refractive error to provide at least a part of the wearer's vision correction. The lens has a prescription based on a wave front analysis of the wearer's eye and the lens can further be modified to fit within an eyeglass frame.
US09500875B2
An imaging lens unit is presented, comprising an imaging lens having a lens region defining an effective aperture, and a phase coder. The phase coder may be incorporated with or located close to the lens region. The phase coder defines a surface relief along the lens region formed by at least three phase patterns extending along the lens region. Each of the phase patterns differently affecting light components of one of at least three different wavelength ranges while substantially not affecting propagation of light components of other of said at least three wavelength ranges. The surface relief affects light propagation through the lens region to extend a depth of focus for at least one of said at least three wavelength ranges.
US09500874B2
A liquid crystal optical element according to the present disclosure includes: a prism array composed of a plurality of prisms that have ridge lines extending in a first direction and are arranged in a second direction orthogonal to the first direction; a liquid crystal layer provided on the prism array; and an electrode via which a voltage is applied to the liquid crystal layer. When the voltage applied to the liquid crystal layer is 0 volt, long axes of liquid crystal molecules of the liquid crystal layer are oriented so as to be inclined at a predetermined angle relative to the first direction in a plane orthogonal to the second direction.
US09500870B2
A beam splitting system for laser ranging includes a roof half-pentaprism, an isosceles prism and a compensating prism. Due to different compensating prisms, there are four light splitting combinations in total. Light of a certain wavelength is incident from one side of the roof half-pentaprism, and is reflected therein for several times and finally emergent into the isosceles prism where it is reflected for several times and finally emergent in a direction consistent with an incident light axis. Light of another wavelength is incident from one side of the compensating prism, and finally emergent from one side of the roof half-pentaprism or one side of the isosceles prism. Different light splitting ways may be caused due to different positions of both prisms and data LCDs. A number of different optical ranging systems will be provided if a laser rangefinder employs different light splitting combinations.
US09500865B2
A method and apparatus may capture an image of a second person with a camera on a frame worn by a user, transmit the image to a second device, receive a recommendation for the user to interact with the second person in response to a behavior of the second person, and display the recommendation to the user on how to interact with the second person in response to the second person's behavior.
US09500864B2
A combiner positioning system for a head-up display includes a carrier and a locking element. The carrier supports a combiner for the head-up display, and the combiner is movable between a stowed position and a display position. The locking element has an engaged position and a disengaged position. The locking element engages a portion of the carrier in the display position and rigidly holds the carrier in the display position.
US09500862B2
Provided is a display information generation apparatus that displays information in a manner so that it becomes possible to immediately and intuitively recognize the information, which is for guiding a mobile body. A navigation apparatus provided with a display that moves together with a vehicle is provided with a display data generation unit that acquires position information indicating the position of the vehicle, acquires, on the basis of the acquired position information, distance information indicating the distance from the position of the vehicle of facilities positioned along the road along which the vehicle is moving, and, on the basis of the acquired position information and distance information, displays an icon indicating the facilities at both sides of the road at the display arranged in order of the order of appearance accompanying the motion of the vehicle.
US09500861B2
A protective member protects an objective lens. The protective member includes an insertion opening through which an objective lens is configured to be inserted and a main body configured to cover the inserted objective lens. The main body includes a side wall portion connected to the insertion opening and a bottom portion connected to the side wall portion as well as facing the insertion opening, and covers the inserted objective lens with the side wall portion and the bottom portion. The protective member further includes a liquid disposed inside the main body, a sealing film body for sealing the insertion opening and a window arranged in the bottom portion of the main body, through which light transmits. The protective member can simplify the work.
US09500855B2
A laser resonator is provided that includes a cavity bounded by an end mirror and output coupler, and one or more gain media between the end mirror and output coupler. The laser resonator also includes a modal corrector mirror between the end mirror and output coupler. The modal corrector mirror includes a controllable-profile faceplate including an optically-treated front surface, and an array of static actuators. Each static actuator includes an adjustable element, and a compliant mechanism located between the adjustable element and faceplate. The adjustable element is configured to exert a selectable, localized push-pull force on the faceplate via the compliant mechanism, and the compliant mechanism is configured to scale the respective force.
US09500846B2
Excitation light is focused to a focus within a sample and the focus is scanned within a volume in the sample with scanning optical elements. Signal light emitted from the focus is de-scanned, with the one or more scanning optical elements, onto a wavefront sensor as the focus is scanned within the volume. Based on the descanned signal light, an average aberration created by the volume of the sample of a wavefront of the excitation light is determined. A wavefront of the excitation light is corrected by an amount according to the determined average aberration while the focus is scanned within the volume, the signal light is imaged onto a photosensitive detector as the focus is scanned within the volume, and a wavefront of the imaged signal light is corrected by an amount according to the determined average aberration while the focus is scanned. These steps can be repeated for a plurality of different volumes in the sample, and an image of the sample can be generated based on the detected signal light from scanned foci within the different volumes.
US09500838B2
A lens driving apparatus for a lens includes a voice coil motor. A coil position of a coil is detected. A table memory stores a correction factor for each one of plural values of the coil position according to flux density distribution. The correction factor is read from the table memory according to the detected coil position. A coil current is corrected by use of the correction factor for each coil position. The corrected coil current is caused to flow through the coil, with which the lens is moved together along an optical axis. Consequently, changes in a moving speed of the lens can be prevented.
US09500832B2
An optical fiber strand holding tool is disclosed for organizing and retaining splice sleeves and fibers from a first fiber bundle during, and optionally after, a splicing activity in which the first bundle is spliced to a second fiber bundle. The apparatus and associated method provide a means of removably securing splice sleeves in an orderly fashion, preventing movement and contamination of the bare fibers during splicing. Magnets and clamping pressure are used separately or in conjunction to provide the retention force. A removable splice retaining portion permits permanent optical joint storage and protection, and reduces handling of the optical joints. Color coded splice sleeves and splice channels are employed for quick matching between fibers in fiber bundle pairs being spliced.
US09500829B2
The present disclosure relates to a fiber optic retention device to properly accommodate for cable management arrangements and schemes in telecommunication infrastructures that are massive in scale and/or require subsequent adaptation of the infrastructures. The device includes a C-shaped opening and a spring biased door which moves inwardly to allow cable entry and exit to the device. In one embodiment, the spring is an integral extension of the door. In another embodiment, the spring is a separate torsion coil spring.
US09500821B2
A photonic interface for an electronic circuit is disclosed. The photonic interface includes a photonic integrated circuit having a modulator and a photodetector, and an optical fiber or fibers for optical communication with another optical circuit. A modulator driver chip may be mounted directly on the photonic integrated circuit. The optical fibers may be placed in v-grooves of a fiber support, which may include at least one lithographically defined alignment feature for optical alignment to the silicon photonic circuit.
US09500816B2
The present disclosure relates to a fiber optic connector and cable assembly. The fiber optic connector and cable assembly includes a fiber optic connector, a fiber optic cable, and an anchoring mechanism. The fiber optic connector includes a connector housing and a ferrule assembly having a ferrule and a spring. The fiber optic cable includes at least one optical fiber contained within a cable jacket and at least one strength structure for providing tensile reinforcement to the fiber optic cable. The fiber optic cable is attached to the fiber optic connector and the at least one optical fiber runs from the fiber optic cable through a total length of the fiber optic connector. The anchor mechanism anchors the at least one optical fiber to at least one of the cable jacket and the at least one strength structure.
US09500812B2
A photoelectric composite connector includes a first fitting member including a first holding member holding at least one first optical fiber, and at least one first electric connecting portion, and a second fitting member including a second holding member holding at least one second optical fiber, and at least one second electric connecting portion. The first and second fitting members are constituted as to fit into and onto each other so that the first and second optical fibers are optically connected and the first and second electric connecting portions are electrically connected. The first and second fitting members includes a protecting section to prevent foreign materials generated during fitting of the first and second fitting members from entering into at least the first and second holding members.
US09500811B2
Disclosed is an optical circuit including a transparent plate, which is light-transmittable, and a light shielding plate, which is adhered to the transparent plate with an adhesive and has an opening through which incident light passes, and in which the aspect facing to the opening has, on the side opposite to the transparent plate, projections in an overhang shape toward the center of the opening.
US09500808B2
A method, system, and apparatus are disclosed for a ruggedized photonic crystal (PC) sensor packaging. In particular, the present disclosure teaches a ruggedized packaging for a photonic crystal sensor that includes of a hermetic-seal high-temperature jacket and a ferrule that eliminate the exposure of the optical fiber as well as the critical part of the photonic crystal sensor to harsh environments. The disclosed packaging methods enable photonic crystal based sensors to operate in challenging environments where adverse environmental conditions, such as electromagnetic interference (EMI), corrosive fluids, large temperature variations, and strong mechanical vibrations, currently exclude the use of traditional sensor technologies.
US09500797B2
The present invention provides a microlens array including multiple microlenses arranged axially parallel to one another, wherein entrance surfaces of the microlenses on which light is incident are made of resin, and exit surfaces of the microlenses from which light exits are made of glass.
US09500791B2
A gradient light halo device gradient light halo device for creating a gradient light halo for a remote input device is disclosed herein. The device includes a backlight portion to project a backlight onto a first surface of a remote input device; a floodlight portion to project a floodlight onto a second surface of the remote input device, the second surface opposing the first surface; an ink layer disposed on the first surface, the ink layer including a solid portion and a stippled portion; and a blocking layer disposed on the second surface, the blocking layer including a non-ink portion and an ink portion. A method of creating a gradient light halo is also disclosed, as well as a method of manufacturing a gradient light halo assembly.
US09500789B2
An array of nanowires with a period smaller then 150 nm can be used for applications such as an optical polarizer. A hard nanomask can be used to manufacture such structures. This nanomask includes a substantially periodic array of substantially parallel elongated elements having a wavelike cross-section. The fabrication method of the nanomask may be contactless and uses ion beams.
US09500786B2
The present invention has been made in an effort to provide a stereoscopic image display comprising: a liquid crystal panel comprising a lower substrate and an upper substrate; RGB color filters positioned on a first surface of the upper substrate; thin film transistors positioned on a first surface of the lower substrate; a black matrix positioned on a second surface of the upper substrate; and a patterned retarder film for separating an image displayed on the liquid crystal panel, wherein at least one of the RGB color filters has a dummy part overlapping at least a portion of one or both of the other color filters.
US09500781B2
An optical system and a laser processing apparatus with which spattering can be suppressed by reducing an evaporation reactive force at a workpiece by forming two focal points on the optical axis, using a simple configuration. The optical system is provided with a convex lens that focuses laser light; and a concave lens that is disposed on the same optical axis as the laser light that passes through the convex lens. The concave lens has a first region that has a through-hole, that is positioned on the optical axis, and that does not have lens properties, as well as a second region that surrounds the first region and that diverges the laser light.
US09500775B2
The invention provide a class of actinically-crosslinkable amphiphilic prepolymers which comprise at least one polysiloxane segment, at least one polyoxazoline segment, and two terminal ene groups. The present invention is also related to a medical device comprising a silicone hydrogel material obtained from step-growth polymerization of a polymerizable material comprising a prepolymer of the invention and to a method for producing contact lenses from a prepolymer of the invention.
US09500771B2
The present disclosure relates to a metamaterial for converging electromagnetic waves, which comprises a plurality of cubic metamaterial units arranged in a first array which takes a y direction as a column direction and a z direction perpendicular to the y direction as a row direction. The metamaterial units of each row have the same refractive index, and for the metamaterial units of each column, the refractive indices thereof for the electromagnetic waves decrease gradually from a middle metamaterial unit towards two ends of the column, with variations of the refractive indices between adjacent ones of the metamaterial units increasing gradually from the middle metamaterial unit towards the two ends of the column; and the metamaterial units are anisotropic to the electromagnetic waves. The metamaterial for converging electromagnetic waves of the present disclosure can achieve the function of converging electromagnetic waves, and has a smaller thickness compared to conventional metamaterials.
US09500764B2
The present disclosure discloses a scanning imaging system, comprising a transportation apparatus, a first imaging system, and a second imaging system. A distance between a ray beam from a first ray generator of the first imaging system and a ray beam from a second ray generator of the second imaging system in the transportation direction is roughly L. A controller is configured to acquire, based on a count value of the encoding counter module, a correspondence relationship between data in a position of the inspected object in the transportation direction which is collected by the first imaging system and data in the position of the inspected object in the transportation direction which is collected by the second imaging system, wherein a difference between a count value of the encoder corresponding to the data in the position which is collected by the first imaging system and a count value of the encoder corresponding to the data in the position which is collected by the second imaging system is roughly L/D. The present disclosure can achieve alignment of the DR data image and the CT data image in a simple manner.
US09500761B2
A technique facilitates obtaining seismic data in a marine environment. An array of acoustic sources is deployed in a marine environment. The array can be utilized for creating acoustic pulses that facilitate the collection of data on subsea structures. The methodology enables optimization of acoustic source array performance to improve the collection of useful data during a seismic survey.
US09500754B2
A neutron scintillator includes a resin composition having a resin and an inorganic phosphor containing at least one kind of neutron-capturing isotope that is selected from lithium 6 and boron 10 such as Eu:LiCaAlF6. The resin composition contains 0.2-30×1018 atom/mm3 of lithium 6 and 0.05-8×1018 atom/mm3 of boron 10 and is in such a form that the average diameter of inscribed spheres is 5 mm or less. A neutron scintillator is formed of a resin-based composite having a plurality of parts formed of the aforesaid resin composition and supplementing part(s), in which the content of the neutron-capturing isotope is not more than ½ of the content of the neutron-capturing isotope in the resin composition. The ratio of the distance between the centers of inscribed spheres in the individual parts formed of the resin composition to the sum of the diameters of the inscribed spheres therein is 1.2 or greater.
