An OTP memory cell (200) including an antifuse unit (206) and a select transistor (208) is provided. The antifuse unit includes an antifuse layer (210) and an antifuse gate (212) disposed on a substrate (202) in sequence, a modified extension doped region (214) disposed in the substrate below the antifuse layer, and a first doped region (216) and a second doped region (218) disposed in the substrate at two opposite sides of the antifuse gate. The select transistor includes a select gate (220) on the substrate, a gate dielectric layer (222) between substrate and select gate, the second doped region (218), and a third doped region (224). The second and the third doped region are respectively disposed in the substrate at two oppositesides of the select gate. The modified extension doped region, the antifuse layer and the antifuse gate form a varactor.