The invention relates to a multifunctional clock buffer suitable for an SRAM type FPGA. The buffer comprises a first clock control circuit B101, a second clock control circuit B102 and an output multiplexer B103; the clock buffer disclosed by the invention is used for driving a global clock network in the FPGA; different working modes are realized according to FPGA configuration; the first working mode is an ordinary clock buffer; the second working mode is an enabled clock buffer; when the clock buffer is not enabled, the output clock is fixed at high level; the third working mode is a clock multiplexer capable of completing burr-free switching of two clocks; the fourth working mode is an enabled clock multiplexer capable of completing burr-free switching of two clocks; and, when the clock multiplexer is not enabled, the output clock is fixed at high level. A buffer circuit additionally provides an input clock slighting control port; and thus, switching operation of a clock can be completed under a condition that the clock is disappeared.