Invention Publication
- Patent Title: Condition code prediction apparatus
- Patent Title (中): 条件码预测装置
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Application No.: EP89100516.7Application Date: 1989-01-13
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Publication No.: EP0328871A3Publication Date: 1991-07-03
- Inventor: Vassiliadis, Stamatis , Putrino, Michael , Huffman, Ann Elizabeth , Feal, Brice John , Pechanek, Gerald George
- Applicant: International Business Machines Corporation
- Applicant Address: Old Orchard Road Armonk, N.Y. 10504 US
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: Old Orchard Road Armonk, N.Y. 10504 US
- Agency: Jost, Ottokarl, Dipl.-Ing.
- Priority: US157500 19880217
- Main IPC: G06F7/02
- IPC: G06F7/02 ; G06F7/50 ; G06F9/32
Abstract:
The described embodiments of the present invention determine when two operands are equivalent directly from the operand without the use of an adder. In one embodiment, conditions for the sum being equal to zero are determined from half sum to carry and transmit operators derived from the input operands. These operands are used in some known types of adders and, thus may be provided from a parallel adder to the condition prediction circuitry. In another emobodiment, the equations for a carry-save-adder are modified to provide a circuit specifically designed for the determination of the condition when the sum of the operands is equal to zero. This sum is equal to zero circuit greatly reduces the gate delay and gate count thus allowing the central processing unit to determine the condition prior to the actual sum of two operands. This allows the CPU to react to the condition more quickly, thus increasing overall system speed.
Public/Granted literature
- EP0328871A2 Condition code prediction apparatus Public/Granted day:1989-08-23
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