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1.发明公开Apparatus for branch prediction for computer instructions 失效SprungvorhersagevorrichtungfürKomputerbefehle。
公开(公告)号：EP0328779A2
公开(公告)日：1989-08-23
申请号：EP88121547.9
申请日：1988-12-23
IPC分类号： G06F9/38
CPC分类号： G06F9/3844
摘要： An apparatus for branch prediction for computer instructions predicts the outcome of an executing branch instruction in response to instruction operands Q, R, and B. The apparatus includes combinatorial logic for predicting a first branch condition, ((Q+R)-B) > 0, or a second branch condition ((Q+R)-B) ≦ 0.
摘要翻译： 用于计算机指令的分支预测装置响应于指令操作数Q，R和B预测执行分支指令的结果。该装置包括用于预测第一分支条件的组合逻辑（（Q + R）-B） 0或第二分支条件（（Q + R）-B）
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公开(公告)号：EP0328871A2
公开(公告)日：1989-08-23
申请号：EP89100516.7
申请日：1989-01-13
发明人： Vassiliadis, Stamatis , Putrino, Michael , Huffman, Ann Elizabeth , Feal, Brice John , Pechanek, Gerald George
CPC分类号： G06F7/57 , G06F7/026 , G06F7/49905 , G06F7/505 , G06F9/30094
摘要： The described embodiments of the present invention determine when two operands are equivalent directly from the operand without the use of an adder. In one embodiment, conditions for the sum being equal to zero are determined from half sum to carry and transmit operators derived from the input operands. These operands are used in some known types of adders and, thus may be provided from a parallel adder to the condition prediction circuitry. In another emobodiment, the equations for a carry-save-adder are modified to provide a circuit specifically designed for the determination of the condition when the sum of the operands is equal to zero. This sum is equal to zero circuit greatly reduces the gate delay and gate count thus allowing the central processing unit to determine the condition prior to the actual sum of two operands. This allows the CPU to react to the condition more quickly, thus increasing overall system speed.
摘要翻译： 本发明的所描述的实施例确定了两个操作数在不使用加法器的情况下直接等效于操作数。 在一个实施例中，等于零的和的条件由半和确定以携带和传送从输入操作数导出的运算符。 这些操作数用于一些已知类型的加法器，并且因此可以从并行加法器提供给条件预测电路。 在另一个实施例中，用于进位保存加法器的方程被修改以提供专门设计用于当操作数的和等于零时确定条件的电路。 该和等于零电路大大减少了门延迟和门数，从而允许中央处理单元确定两个操作数的实际总和之前的状态。 这样就可以使CPU更快地对状况作出反应，从而提高整体系统的速度。
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3.发明公开Method for executing speculative load instructions in high-performance processors 失效一种用于在高性能处理器执行推测性装入指令的方法
公开(公告)号：EP0789299A1
公开(公告)日：1997-08-13
申请号：EP97300492.2
申请日：1997-01-27
IPC分类号： G06F9/38
CPC分类号： G06F9/30043 , G06F9/383 , G06F9/3842
摘要： A method for selectively executing speculative load instructions in a high-performance processor is disclosed. In accordance with the present disclosure, when a speculative load instruction for which the data is not stored in a data cache is encountered, a bit within an enable speculative load table which is associated with that particular speculative load instruction is read (62) in order to determine a state of the bit. If the associated bit is in a first state, data for the speculative load instruction is requested (66) from a system bus and further execution of the speculative load instruction is then suspended (68) to wait for control signals from a branch processing unit. If the associated bit is in a second state, the execution of the speculative load instruction is immediately suspended (74) to wait for control signals from the branch processing unit. If the speculative load instruction is executed in response to the control signals, then the associated bit in the enable speculative load table will be set (80) to the first state. However, if the speculative load instruction is not executed in response to the control signals, then the associated bit in the enable speculative load table is set (72) to the second state. In this manner, the displacement of useful data in the data cache due to wrongful execution of the speculative load instruction is avoided.
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公开(公告)号：EP0328779A3
公开(公告)日：1992-01-02
申请号：EP88121547.9
申请日：1988-12-23
IPC分类号： G06F9/38
CPC分类号： G06F9/3844
摘要： An apparatus for branch prediction for computer instructions predicts the outcome of an executing branch instruction in response to instruction operands Q, R, and B. The apparatus includes combinatorial logic for predicting a first branch condition, ((Q+R)-B) > 0, or a second branch condition ((Q+R)-B) ≦ 0.
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公开(公告)号：EP0339305A3
公开(公告)日：1991-07-03
申请号：EP89105855.4
申请日：1989-04-04
IPC分类号： G06F11/10
摘要： An apparatus for predicting parity of a result produced by selection of the most or least significant thirty-two bits produced by a thirty-four bit adder, the parity being predicted concurrently with and independently of the result. Parity for byte Si of the selected result is derived by circuitry implementing the relationship:
Pi = yP(M,n-1) V P(n,M+7) V y′P(M+8, n+7)
in which Pi is the parity bit for Si, y is the positive sense of a signal indicating selection, of the most significant thirty-two result bits, y′ is the complement of y and indicates selection of the least significant thirty-two result bits, P(M,n-1) is parity over the two most significant result bits in the portion of the result covering result bits m through n+7, P(m+8, n+7) is parity of the two least significant bits of the result portion, P(n, m+7) is parity over the central bits of the portion, i is an integer and 0≦i≦3, m=8i, and n=m+2.-
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公开(公告)号：EP0296457A3
公开(公告)日：1991-07-17
申请号：EP88109439.5
申请日：1988-06-14
IPC分类号： G06F7/50
CPC分类号： G06F7/505 , G06F2207/382
摘要： A parallel binary byte adder performs addition and subtraction on the individual bytes of an A-operand (10) and a B-operand (12) as well as on the entire A and B operand. An A-operand is input to a special adder circuit (20). A B-operand is modified in a set up logic circuit (14), in accordance with the specific operation to be performed, before being input to the special adder circuit (20). A set/mask logic (18) generates set, mask and carry signals which are further input to the special adder circuit (20). The special adder circuit (20) includes an auxiliary functions circuit (20a) and a pseudo carry circuit (20b) for generating a set of "variables" in response to the A-operand (10), the modified B-operand (16), and the output of the set/mask logic (18). The special adder circuit (20) further includes a sum circuit (20c) which is implemented from three separate Boolean equations, the equations being a function of the "variables". The first Boolean equation relates to bits 0-5 of a particular byte of the A-operand (10) and the modified B-operand (16) undergoing addition or subtraction. The second Boolean equation relates to bit 6 of the particular byte, and the third Boolean equation relates to bit 7 of the particular byte. The special adder (20) is responsive to the A-operand (10), the modified B-operand (16), an output of the set of logic (14), and an output of the Set/Mask logic (18) for performing an operation on bits 0-5 of a particular byte, associated with the A-operand (10) and the modified B-operand (16) undergoing addition or subtraction, performing an operation on bit 6 of the particular byte of the A-operand (10) and modified B-operand (16), performing an operation on bit 7 of the particular byte of the A-operand (10) and modified B-operand (16), and concatenating the results of the operations associated with bits 0-5, bit 6, and bit 7 of the particular byte of the A-operand (10) and the modified B-operand (16). The concatenated results represent the sum or difference of the particular byte associated with the A-operand (10) and the modified B-operand (16).
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公开(公告)号：EP0328871A3
公开(公告)日：1991-07-03
申请号：EP89100516.7
申请日：1989-01-13
发明人： Vassiliadis, Stamatis , Putrino, Michael , Huffman, Ann Elizabeth , Feal, Brice John , Pechanek, Gerald George
CPC分类号： G06F7/57 , G06F7/026 , G06F7/49905 , G06F7/505 , G06F9/30094
摘要： The described embodiments of the present invention determine when two operands are equivalent directly from the operand without the use of an adder. In one embodiment, conditions for the sum being equal to zero are determined from half sum to carry and transmit operators derived from the input operands. These operands are used in some known types of adders and, thus may be provided from a parallel adder to the condition prediction circuitry. In another emobodiment, the equations for a carry-save-adder are modified to provide a circuit specifically designed for the determination of the condition when the sum of the operands is equal to zero. This sum is equal to zero circuit greatly reduces the gate delay and gate count thus allowing the central processing unit to determine the condition prior to the actual sum of two operands. This allows the CPU to react to the condition more quickly, thus increasing overall system speed.
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9.发明公开Parity prediction for binary adders with selection 失效ParitätsvorausbestimmungfürBinäraddierermit Auswahl。
公开(公告)号：EP0339305A2
公开(公告)日：1989-11-02
申请号：EP89105855.4
申请日：1989-04-04
IPC分类号： G06F11/10
摘要： An apparatus for predicting parity of a result produced by selection of the most or least significant thirty-two bits produced by a thirty-four bit adder, the parity being predicted concurrently with and independently of the result. Parity for byte Si of the selected result is derived by circuitry implementing the relationship:
Pi = yP(M,n-1) V P(n,M+7) V y′P(M+8, n+7)
in which Pi is the parity bit for Si, y is the positive sense of a signal indicating selection, of the most significant thirty-two result bits, y′ is the complement of y and indicates selection of the least significant thirty-two result bits, P(M,n-1) is parity over the two most significant result bits in the portion of the result covering result bits m through n+7, P(m+8, n+7) is parity of the two least significant bits of the result portion, P(n, m+7) is parity over the central bits of the portion, i is an integer and 0≦i≦3, m=8i, and n=m+2.摘要翻译： 一种用于通过选择由三十四位加法器产生的最大或最不重要的三十二位产生的结果的奇偶校验的装置，所述奇偶校验与结果同时且独立地被预测。 所选结果的字节Si的奇偶校验通过实现以下关系的电路得到：Pi = yP（M，n-1）VP（n，M + 7）V y min P（M + 8，n + 7） 是Si的奇偶校验位，y是指示选择的信号的正向，最显着的32个结果位，y min是y的补码，并且指示选择最不重要的32个结果位P（ M，n-1）是覆盖结果位m至n + 7的结果部分中两个最高有效结果位的奇偶校验，P（m + 8，n + 7）是两个最低有效位的奇偶校验 结果部分，P（n，m + 7）是该部分的中心位上的奇偶校验，i是整数，0 = i i = 3，m = 8i，n = m + 2。
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公开(公告)号：EP0296457A2
公开(公告)日：1988-12-28
申请号：EP88109439.5
申请日：1988-06-14
IPC分类号： G06F7/50
CPC分类号： G06F7/505 , G06F2207/382
摘要： A parallel binary byte adder performs addition and subtraction on the individual bytes of an A-operand (10) and a B-operand (12) as well as on the entire A and B operand. An A-operand is input to a special adder circuit (20). A B-operand is modified in a set up logic circuit (14), in accordance with the specific operation to be performed, before being input to the special adder circuit (20). A set/mask logic (18) generates set, mask and carry signals which are further input to the special adder circuit (20). The special adder circuit (20) includes an auxiliary functions circuit (20a) and a pseudo carry circuit (20b) for generating a set of "variables" in response to the A-operand (10), the modified B-operand (16), and the output of the set/mask logic (18). The special adder circuit (20) further includes a sum circuit (20c) which is implemented from three separate Boolean equations, the equations being a function of the "variables". The first Boolean equation relates to bits 0-5 of a particular byte of the A-operand (10) and the modified B-operand (16) undergoing addition or subtraction. The second Boolean equation relates to bit 6 of the particular byte, and the third Boolean equation relates to bit 7 of the particular byte. The special adder (20) is responsive to the A-operand (10), the modified B-operand (16), an output of the set of logic (14), and an output of the Set/Mask logic (18) for performing an operation on bits 0-5 of a particular byte, associated with the A-operand (10) and the modified B-operand (16) undergoing addition or subtraction, performing an operation on bit 6 of the particular byte of the A-operand (10) and modified B-operand (16), performing an operation on bit 7 of the particular byte of the A-operand (10) and modified B-operand (16), and concatenating the results of the operations associated with bits 0-5, bit 6, and bit 7 of the particular byte of the A-operand (10) and the modified B-operand (16). The concatenated results represent the sum or difference of the particular byte associated with the A-operand (10) and the modified B-operand (16).
摘要翻译： 并行二进制字节加法器对A操作数（10）和B操作数（12）的各个字节以及整个A和B操作数执行加法和减法。 一个A操作数被输入到一个特殊的加法器电路（20）。 在输入到特殊加法器电路（20）之前，根据要执行的具体操作，在建立逻辑电路（14）中修改B操作数。 置位/屏蔽逻辑（18）产生进一步输入到特殊加法器电路（20）的置位，屏蔽和进位信号。 特殊加法器电路（20）包括用于响应A操作数（10），修改的B操作数（16）产生一组“变量”的辅助功能电路（20a）和伪进位电路（20b） ，以及置位/屏蔽逻辑（18）的输出。 特殊加法器电路（20）还包括一个和电路（20c），它由三个独立的布尔等式实现，等式是“变量”的函数。 第一布尔等式涉及A操作数（10）的特定字节的位0-5和经历加法或减法的修改的B操作数（16）。 第二个布尔方程涉及特定字节的第6位，第三个布尔方程涉及特定字节的第7位。 特殊加法器（20）响应于A操作数（10），修改的B操作数（16），逻辑组（14）的输出以及设置/屏蔽逻辑（18）的输出 对与A操作数（10）和修改的B操作数（16）相关联的特定字节的位0-5执行加或减的操作，在A位的特定字节的位6上执行操作， 操作数（10）和修改的B操作数（16），对A操作数（10）和修改的B操作数（16）的特定字节的位7执行操作，并且将与位 （10）的特定字节的0-5，位6和位7以及修改的B操作数（16）。 级联结果表示与A操作数（10）和修改的B操作数（16）相关的特定字节的和或差。
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