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1.发明公开Apparatus for branch prediction for computer instructions 失效SprungvorhersagevorrichtungfürKomputerbefehle。
公开(公告)号：EP0328779A2
公开(公告)日：1989-08-23
申请号：EP88121547.9
申请日：1988-12-23
IPC分类号： G06F9/38
CPC分类号： G06F9/3844
摘要： An apparatus for branch prediction for computer instructions predicts the outcome of an executing branch instruction in response to instruction operands Q, R, and B. The apparatus includes combinatorial logic for predicting a first branch condition, ((Q+R)-B) > 0, or a second branch condition ((Q+R)-B) ≦ 0.
摘要翻译： 用于计算机指令的分支预测装置响应于指令操作数Q，R和B预测执行分支指令的结果。该装置包括用于预测第一分支条件的组合逻辑（（Q + R）-B） 0或第二分支条件（（Q + R）-B）
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公开(公告)号：EP0328779A3
公开(公告)日：1992-01-02
申请号：EP88121547.9
申请日：1988-12-23
IPC分类号： G06F9/38
CPC分类号： G06F9/3844
摘要： An apparatus for branch prediction for computer instructions predicts the outcome of an executing branch instruction in response to instruction operands Q, R, and B. The apparatus includes combinatorial logic for predicting a first branch condition, ((Q+R)-B) > 0, or a second branch condition ((Q+R)-B) ≦ 0.
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公开(公告)号：EP0328871A3
公开(公告)日：1991-07-03
申请号：EP89100516.7
申请日：1989-01-13
发明人： Vassiliadis, Stamatis , Putrino, Michael , Huffman, Ann Elizabeth , Feal, Brice John , Pechanek, Gerald George
CPC分类号： G06F7/57 , G06F7/026 , G06F7/49905 , G06F7/505 , G06F9/30094
摘要： The described embodiments of the present invention determine when two operands are equivalent directly from the operand without the use of an adder. In one embodiment, conditions for the sum being equal to zero are determined from half sum to carry and transmit operators derived from the input operands. These operands are used in some known types of adders and, thus may be provided from a parallel adder to the condition prediction circuitry. In another emobodiment, the equations for a carry-save-adder are modified to provide a circuit specifically designed for the determination of the condition when the sum of the operands is equal to zero. This sum is equal to zero circuit greatly reduces the gate delay and gate count thus allowing the central processing unit to determine the condition prior to the actual sum of two operands. This allows the CPU to react to the condition more quickly, thus increasing overall system speed.
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公开(公告)号：EP0328871A2
公开(公告)日：1989-08-23
申请号：EP89100516.7
申请日：1989-01-13
发明人： Vassiliadis, Stamatis , Putrino, Michael , Huffman, Ann Elizabeth , Feal, Brice John , Pechanek, Gerald George
CPC分类号： G06F7/57 , G06F7/026 , G06F7/49905 , G06F7/505 , G06F9/30094
摘要： The described embodiments of the present invention determine when two operands are equivalent directly from the operand without the use of an adder. In one embodiment, conditions for the sum being equal to zero are determined from half sum to carry and transmit operators derived from the input operands. These operands are used in some known types of adders and, thus may be provided from a parallel adder to the condition prediction circuitry. In another emobodiment, the equations for a carry-save-adder are modified to provide a circuit specifically designed for the determination of the condition when the sum of the operands is equal to zero. This sum is equal to zero circuit greatly reduces the gate delay and gate count thus allowing the central processing unit to determine the condition prior to the actual sum of two operands. This allows the CPU to react to the condition more quickly, thus increasing overall system speed.
摘要翻译： 本发明的所描述的实施例确定了两个操作数在不使用加法器的情况下直接等效于操作数。 在一个实施例中，等于零的和的条件由半和确定以携带和传送从输入操作数导出的运算符。 这些操作数用于一些已知类型的加法器，并且因此可以从并行加法器提供给条件预测电路。 在另一个实施例中，用于进位保存加法器的方程被修改以提供专门设计用于当操作数的和等于零时确定条件的电路。 该和等于零电路大大减少了门延迟和门数，从而允许中央处理单元确定两个操作数的实际总和之前的状态。 这样就可以使CPU更快地对状况作出反应，从而提高整体系统的速度。
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