发明公开
EP0338817A3 Semiconductor integrated circuit device and method of producing the same using master slice approach
失效
半导体集成电路装置及其使用主狭缝方法生产相同方法
- 专利标题： Semiconductor integrated circuit device and method of producing the same using master slice approach
- 专利标题（中）： 半导体集成电路装置及其使用主狭缝方法生产相同方法
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申请号： EP89303912.3申请日： 1989-04-20
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公开(公告)号： EP0338817A3公开(公告)日： 1992-05-06
- 发明人: Hirose, Yoshio , Yamashita, Koichi , Kawahara, Shigeki , Sato, Shinji , Sasaki, Takeshi , Kumagai, Ataru
- 申请人： FUJITSU LIMITED
- 申请人地址： 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi, Kanagawa 211 JP
- 专利权人： FUJITSU LIMITED
- 当前专利权人： FUJITSU LIMITED
- 当前专利权人地址： 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi, Kanagawa 211 JP
- 代理机构： Stebbing, Timothy Charles
- 优先权： JP100631/88 19880422; JP180953/88 19880720; JP180954/88 19880720
- 主分类号： H01L27/02
- IPC分类号： H01L27/02 ; H01L23/52 ; H01L21/82
摘要：
A semiconductor integrated circuit device includes: a master chip(203) including a basic cell region(201) having a plurality of basic cell arrays(206) arranged thereon, and an input/output cell region(202) having a plurality of input/output cells(207) arranged along the periphery of the basic cell region; a first wiring layer formed on the basic cell region and the input/output cell region via a first insulation layer having contact holes at predetermined positions, the first wiring layer including fixed wirings(LA,508); and a second wiring layer formed on the first wiring layer via a second insulation layer having through holes at predetermined positions, the second wiring layer including programmed wirings(LB,507). Only the wiring pattern of the second wiring layer is suitably changed in accordance with conditions of circuits applied to the input/output cell region and the basic cell region in regions corresponding to the input/output cell region and the basic cell region, thereby greatly reducing a turnaround time of the device.
公开/授权文献
- EP0338817B1 Master slice semiconductor integrated circuit device 公开/授权日：1999-09-08
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