公开(公告)号：EP0871071A3

公开(公告)日：2000-04-19

申请号：EP97308800.8

申请日：1997-11-03

申请人： FUJITSU LIMITED ,  Advantest Corporation

发明人： Kawakami, Kenichi ,  Susa, Masahiko ,  Yamashita, Koichi ,  Katsuhiko, Kobayashi ,  Yamada, Akio ,  Nishio, Naoki

IPC分类号： G03F7/20 ,  H01J37/302

CPC分类号： H01J37/3023 ,  H01J2237/31766

摘要： The present invention is a method of charged particle beam exposure wherein an area of an exposure pattern is exposed by irradiating a sample (36) with a charged particle beam while moving said sample, comprising: a step of generating speed data including the speed distribution in a direction of movement of the sample in accordance with secondary data which is generated from a pattern data including at least data (37) of the exposure pattern and data (38) of an exposure position, and includes at least density information of the exposure pattern; and a step of irradiating the sample (36) with the charged particle beam in accordance with the pattern data while being moved at variable speed in accordance with the speed data. According to the invention, the through-put is improved very much without any defect of the exposure.

摘要翻译： 本发明是一种带电粒子束曝光的方法，其中通过在移动所述样品的同时照射具有带电粒子束的样品（36）来曝光曝光图案的区域，包括：产生包括速度分布的速度数据的步骤 根据从包括曝光图案的数据（37）和曝光位置的数据（38））的图案数据生成的二次数据的样本的移动方向，并且至少包括曝光图案的浓度信息 ; 以及根据速度数据以可变速度移动，根据图案数据照射具有带电粒子束的样品（36）的步骤。 根据本发明，绝对改善非常大，没有任何曝光缺陷。

公开(公告)号：EP0871071A2

公开(公告)日：1998-10-14

申请号：EP97308800.8

申请日：1997-11-03

申请人： FUJITSU LIMITED ,  Advantest Corporation

发明人： Kawakami, Kenichi ,  Susa, Masahiko ,  Yamashita, Koichi ,  Katsuhiko, Kobayashi ,  Yamada, Akio ,  Nishio, Naoki

IPC分类号： G03F7/20

CPC分类号： H01J37/3023 ,  H01J2237/31766

摘要： The present invention is a method of charged particle beam exposure wherein an area of an exposure pattern is exposed by irradiating a sample (36) with a charged particle beam while moving said sample, comprising: a step of generating speed data including the speed distribution in a direction of movement of the sample in accordance with secondary data which is generated from a pattern data including at least data (37) of the exposure pattern and data (38) of an exposure position, and includes at least density information of the exposure pattern; and a step of irradiating the sample (36) with the charged particle beam in accordance with the pattern data while being moved at variable speed in accordance with the speed data. According to the invention, the through-put is improved very much without any defect of the exposure.

摘要翻译： 本发明是一种带电粒子束曝光的方法，其中通过在移动所述样品的同时照射具有带电粒子束的样品（36）来曝光曝光图案的区域，包括：产生包括速度分布的速度数据的步骤 根据从包括曝光图案的数据（37）和曝光位置的数据（38））的图案数据生成的二次数据的样本的移动方向，并且至少包括曝光图案的浓度信息 ; 以及根据速度数据以可变速度移动，根据图案数据照射具有带电粒子束的样品（36）的步骤。 根据本发明，绝对改善非常大，没有任何曝光缺陷。

公开(公告)号：EP0368625A3

公开(公告)日：1991-07-03

申请号：EP89311525.3

申请日：1989-11-07

申请人： FUJITSU LIMITED

发明人： Ohe, Ryoichi ,  Yamashita, Koichi

IPC分类号： G06F17/50

CPC分类号： H01L27/11807 ,  G06F17/5068

摘要： A method and an apparatus is provided for forming a layout pattern of a semiconductor integrated circuit comprising a step or a means for automatically reforming a layout pattern by only carrying out a routing process, when a required layout pattern is the same as an existing layout pattern at the transistor-­constitution level. Further, a method or an apparatus is provided for forming a layout pattern of a semiconductor integrated circuit comprising a step or a means for automatically reforming a layout pattern without analyzing the logical information down to the transistor-constitution level, when a required layout pattern is not the same as an existing layout pattern in the transistor-constitution level. Therefore, processing can be simplified and operation speed can be increased.

公开(公告)号：EP0338817B1

公开(公告)日：1999-09-08

申请号：EP89303912.3

申请日：1989-04-20

申请人： FUJITSU LIMITED

发明人： Hirose, Yoshio ,  Yamashita, Koichi ,  Kawahara, Shigeki ,  Sato, Shinji ,  Sasaki, Takeshi ,  Kumagai, Ataru

IPC分类号： H01L27/02 ,  H01L23/52 ,  H01L21/82

CPC分类号： H01L23/528 ,  H01L21/82 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP0338817A3

公开(公告)日：1992-05-06

申请号：EP89303912.3

申请日：1989-04-20

申请人： FUJITSU LIMITED

发明人： Hirose, Yoshio ,  Yamashita, Koichi ,  Kawahara, Shigeki ,  Sato, Shinji ,  Sasaki, Takeshi ,  Kumagai, Ataru

IPC分类号： H01L27/02 ,  H01L23/52 ,  H01L21/82

CPC分类号： H01L23/528 ,  H01L21/82 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit device includes: a master chip(203) including a basic cell region(201) having a plurality of basic cell arrays(206) arranged thereon, and an input/output cell region(202) having a plurality of input/output cells(207) arranged along the periphery of the basic cell region; a first wiring layer formed on the basic cell region and the input/output cell region via a first insulation layer having contact holes at predetermined positions, the first wiring layer including fixed wirings(LA,508); and a second wiring layer formed on the first wiring layer via a second insulation layer having through holes at predetermined positions, the second wiring layer including programmed wirings(LB,507). Only the wiring pattern of the second wiring layer is suitably changed in accordance with conditions of circuits applied to the input/output cell region and the basic cell region in regions corresponding to the input/output cell region and the basic cell region, thereby greatly reducing a turnaround time of the device.

公开(公告)号：EP0273821A3

公开(公告)日：1990-03-28

申请号：EP87402872.3

申请日：1987-12-15

申请人： FUJITSU LIMITED

发明人： Yamashita, Koichi

IPC分类号： G01R31/28

CPC分类号： G01R31/318335 ,  G01R31/318385 ,  G01R31/318547 ,  G01R31/318558 ,  G06F11/27

摘要： A semiconductor integrated circuit comprises a plurality of integrated circuit blocks (31 - 39) constituted on a wafer (30), the integrated circuit blocks being arbitrarily electrically connected to each other so as to form a system. Each of the integrated circuit blocks comprises a logical operating circuit (42) for carrying out a logical operation; a pseudo-random pattern generating circuit (40) for generating a pseudo-random pattern signal; switching circuit (41) for selecting either an input signal to be processed by the logical operating circuit or the pseudo-random pattern signal in response to a test enabling signal (TE1 - TE9) which is independently applied to each integrated circuit block so that each integrated circuit block is independently set to either a test mode or a normal mode and for outputting the selected signal to the logical operating circuit; and a data compressing circuit (43) for compressing an output data signal of the logical operating circuit.

公开(公告)号：EP0368625B1

公开(公告)日：1995-03-08

申请号：EP89311525.3

申请日：1989-11-07

申请人： FUJITSU LIMITED

发明人： Ohe, Ryoichi ,  Yamashita, Koichi

IPC分类号： G06F17/50

CPC分类号： H01L27/11807 ,  G06F17/5068

公开(公告)号：EP0273821B1

公开(公告)日：1994-10-19

申请号：EP87402872.3

申请日：1987-12-15

申请人： FUJITSU LIMITED

发明人： Yamashita, Koichi

IPC分类号： G01R31/28

CPC分类号： G01R31/318335 ,  G01R31/318385 ,  G01R31/318547 ,  G01R31/318558 ,  G06F11/27

公开(公告)号：EP0368625A2

公开(公告)日：1990-05-16

申请号：EP89311525.3

申请日：1989-11-07

申请人： FUJITSU LIMITED

发明人： Ohe, Ryoichi ,  Yamashita, Koichi

IPC分类号： G06F17/50

CPC分类号： H01L27/11807 ,  G06F17/5068

摘要： A method and an apparatus is provided for forming a layout pattern of a semiconductor integrated circuit comprising a step or a means for automatically reforming a layout pattern by only carrying out a routing process, when a required layout pattern is the same as an existing layout pattern at the transistor-­constitution level. Further, a method or an apparatus is provided for forming a layout pattern of a semiconductor integrated circuit comprising a step or a means for automatically reforming a layout pattern without analyzing the logical information down to the transistor-constitution level, when a required layout pattern is not the same as an existing layout pattern in the transistor-constitution level. Therefore, processing can be simplified and operation speed can be increased.

摘要翻译： 提供了一种用于形成半导体集成电路的布局图案的方法和装置，该半导体集成电路包括用于通过仅进行布线过程自动重新布局图案的步骤或装置，当所需布局图案与现有布局图案相同时 在晶体管结构水平。 此外，提供了一种用于形成半导体集成电路的布局图案的方法或装置，该半导体集成电路包括用于自动重排布局图案的步骤或装置，而不需要将逻辑信息分析直到晶体管结构水平，当所需的布局图案为 与晶体管结构水平中的现有布局图案不同。 因此，可以简化处理并且可以提高操作速度。

公开(公告)号：EP0338817A2

公开(公告)日：1989-10-25

申请号：EP89303912.3

申请日：1989-04-20

申请人： FUJITSU LIMITED

发明人： Hirose, Yoshio ,  Yamashita, Koichi ,  Kawahara, Shigeki ,  Sato, Shinji ,  Sasaki, Takeshi ,  Kumagai, Ataru

IPC分类号： H01L27/02 ,  H01L23/52 ,  H01L21/82

CPC分类号： H01L23/528 ,  H01L21/82 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit device includes: a master chip(203) including a basic cell region(201) having a plurality of basic cell arrays(206) arranged thereon, and an input/output cell region(202) having a plurality of input/output cells(207) arranged along the periphery of the basic cell region; a first wiring layer formed on the basic cell region and the input/output cell region via a first insulation layer having contact holes at predetermined positions, the first wiring layer including fixed wirings(LA,508); and a second wiring layer formed on the first wiring layer via a second insulation layer having through holes at predetermined positions, the second wiring layer including programmed wirings(LB,507). Only the wiring pattern of the second wiring layer is suitably changed in accordance with conditions of circuits applied to the input/output cell region and the basic cell region in regions corresponding to the input/output cell region and the basic cell region, thereby greatly reducing a turnaround time of the device.

摘要翻译： 一种半导体集成电路器件，包括：主芯片（203），包括具有布置在其上的多个基本单元阵列（206）的基本单元区域（201），以及具有多个输入/ 输出单元（207），沿着基本单元区域的周边布置; 经由具有在预定位置具有接触孔的第一绝缘层形成在基本单元区域和输入/输出单元区域上的第一布线层，第一布线层包括固定布线（LA，508）; 以及第二布线层，其经由在预定位置具有通孔的第二绝缘层形成在所述第一布线层上，所述第二布线层包括编程布线（LB，507）。 根据与输入/输出单元区域和基本单元区域对应的区域中的输入/输出单元区域和基本单元区域的电路的条件适当地改变第二布线层的布线图案，从而大大降低 设备的周转时间。