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    Semiconductor integrated circuit device and method of producing the same using master slice approach
    2.
    发明公开
    Semiconductor integrated circuit device and method of producing the same using master slice approach 失效
    半导体集成电路装置及其使用主狭缝方法生产相同方法

    公开(公告)号：EP0338817A3

    公开(公告)日：1992-05-06

    申请号：EP89303912.3

    申请日：1989-04-20

    申请人： FUJITSU LIMITED

    发明人： Hirose, Yoshio ,  Yamashita, Koichi ,  Kawahara, Shigeki ,  Sato, Shinji ,  Sasaki, Takeshi ,  Kumagai, Ataru

    IPC分类号： H01L27/02 ,  H01L23/52 ,  H01L21/82

    CPC分类号： H01L23/528 ,  H01L21/82 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor integrated circuit device includes: a master chip(203) including a basic cell region(201) having a plurality of basic cell arrays(206) arranged thereon, and an input/output cell region(202) having a plurality of input/output cells(207) arranged along the periphery of the basic cell region; a first wiring layer formed on the basic cell region and the input/output cell region via a first insulation layer having contact holes at predetermined positions, the first wiring layer including fixed wirings(LA,508); and a second wiring layer formed on the first wiring layer via a second insulation layer having through holes at predetermined positions, the second wiring layer including programmed wirings(LB,507). Only the wiring pattern of the second wiring layer is suitably changed in accordance with conditions of circuits applied to the input/output cell region and the basic cell region in regions corresponding to the input/output cell region and the basic cell region, thereby greatly reducing a turnaround time of the device.

    Chip on chip type integrated circuit device
    4.
    发明公开
    Chip on chip type integrated circuit device 失效
    Integrierte Schaltung vom Chip-auf-Chip-Typ。

    公开(公告)号：EP0174224A1

    公开(公告)日：1986-03-12

    申请号：EP85401535.1

    申请日：1985-07-25

    申请人： FUJITSU LIMITED

    发明人： Enomoto, Yoshinori ,  Monma, Hideo ,  Ohta, Shunzo ,  Sasaki, Takeshi

    IPC分类号： G01R31/28 ,  G01R31/02

    CPC分类号： H01L25/0657 ,  G01R31/2853 ,  G01R31/318505 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/06596 ,  H01L2924/01078 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/16195 ,  H01L2924/3011 ,  H01L2924/00014

    摘要： 57 A chip on chip type IC is provided with a checking circuit to check electrically the perfectness of bondings (1-n) between the upper chip (B) and the lower chip (A). The checking circuit is composed of two types of circuits, one checks the group of bonding pairs (1-n) which transfers the signals from the lower chip to the upper chip, and the other one checks a second group of bonding pairs which transfers the signals from the upper chip to the lower chip. By means of a control signal supplied to a control terminal (18), the checking circuit is switched to an operation mode or to a checking mode. In the operation mode, the checking circuit is separated from the inner circuit or the lower chip and the IC operates normally. In the checking mode, test signals applied to test terminals (17) are transferred to the upper chip (B) and sent back to the lower chip (A), to be compared with the original test signals, thus enabling the perfectness of the bondings to be checked from the lower chip side.

    摘要翻译： 片上芯片型IC具有检查电路，以电检查上芯片（B）和下芯片（A）之间的结合（1-n）的完美性。 检查电路由两种类型的电路组成，它们检查将信号从下部芯片传送到上部芯片的绑定对（1-n）组，另一个检查传送信号的第二组键合对 从上芯片到下芯片。 通过提供给控制端子（18）的控制信号，将检查电路切换到操作模式或检查模式。 在操作模式中，检查电路与内部电路或下部芯片分离，并且IC正常工作。 在检查模式下，施加到测试端子（17）的测试信号被传送到上芯片（B）并发回到下芯片（A），以与原始测试信号进行比较，从而使得焊接的完美性 从下面的芯片侧进行检查。

    Semiconductor integrated circuit device and method of producing the same using master slice approach
    5.
    发明公开
    Semiconductor integrated circuit device and method of producing the same using master slice approach 失效
    Integrierte Halbleiterschaltungsanordnung vom“Masterslice”-Typ und Herstellungsverfahrendafür。

    公开(公告)号：EP0338817A2

    公开(公告)日：1989-10-25

    申请号：EP89303912.3

    申请日：1989-04-20

    申请人： FUJITSU LIMITED

    发明人： Hirose, Yoshio ,  Yamashita, Koichi ,  Kawahara, Shigeki ,  Sato, Shinji ,  Sasaki, Takeshi ,  Kumagai, Ataru

    IPC分类号： H01L27/02 ,  H01L23/52 ,  H01L21/82

    CPC分类号： H01L23/528 ,  H01L21/82 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor integrated circuit device includes: a master chip(203) including a basic cell region(201) having a plurality of basic cell arrays(206) arranged thereon, and an input/output cell region(202) having a plurality of input/output cells(207) arranged along the periphery of the basic cell region; a first wiring layer formed on the basic cell region and the input/output cell region via a first insulation layer having contact holes at predetermined positions, the first wiring layer including fixed wirings(LA,508); and a second wiring layer formed on the first wiring layer via a second insulation layer having through holes at predetermined positions, the second wiring layer including programmed wirings(LB,507). Only the wiring pattern of the second wiring layer is suitably changed in accordance with conditions of circuits applied to the input/output cell region and the basic cell region in regions corresponding to the input/output cell region and the basic cell region, thereby greatly reducing a turnaround time of the device.

    摘要翻译： 一种半导体集成电路器件，包括：主芯片（203），包括具有布置在其上的多个基本单元阵列（206）的基本单元区域（201），以及具有多个输入/ 输出单元（207），沿着基本单元区域的周边布置; 经由具有在预定位置具有接触孔的第一绝缘层形成在基本单元区域和输入/输出单元区域上的第一布线层，第一布线层包括固定布线（LA，508）; 以及第二布线层，其经由在预定位置具有通孔的第二绝缘层形成在所述第一布线层上，所述第二布线层包括编程布线（LB，507）。 根据与输入/输出单元区域和基本单元区域对应的区域中的输入/输出单元区域和基本单元区域的电路的条件适当地改变第二布线层的布线图案，从而大大降低 设备的周转时间。

    Semiconductor integrated circuit having a test circuit
    6.
    发明公开
    Semiconductor integrated circuit having a test circuit 失效
    Integrierte Halbleiterschaltung mit Testschaltung。

    公开(公告)号：EP0255449A1

    公开(公告)日：1988-02-03

    申请号：EP87401789.0

    申请日：1987-07-30

    申请人： FUJITSU LIMITED

    发明人： Sasaki, Takeshi ,  Monma, Hideo

    IPC分类号： G01R31/28

    CPC分类号： G01R31/3185

    摘要： A semiconductor device comprises a test signal generating circuit (12) for generating a test signal having an arbitrary frequency, a first buffer (13) for selectively outputting one of the test signal and an external input signal at least one test circuit (15) supplied with an output signal of the first buffer (13), an external output terminal (30), a logic circuit (14), a second buffer (16) for selectively supplying to the external terminal (30) one of the test signals from the test circuit (15) and an output signal of the logic circuit (14), and a switching 10 signal generating circuit (11) for generating switching signals for the first and second buffers (13,16). The state of the test circuit (15) is checked by use of the test signal to indirectly determine the state of the logic circuit (14).

    摘要翻译： 半导体器件包括用于产生具有任意频率的测试信号的测试信号发生电路（12），用于选择性地输出测试信号和外部输入信号之一的第一缓冲器（13），至少提供一个测试电路（15） 具有第一缓冲器（13）的输出信号，外部输出端子（30），逻辑电路（14），第二缓冲器（16），用于选择性地向外部端子（30）提供来自 测试电路（15）和逻辑电路（14）的输出信号，以及用于产生第一和第二缓冲器（13,16）的切换信号的开关10信号发生电路（11）。 通过使用测试信号来检查测试电路（15）的状态，以间接确定逻辑电路（14）的状态。