公开(公告)号：EP0338817A2

公开(公告)日：1989-10-25

申请号：EP89303912.3

申请日：1989-04-20

申请人： FUJITSU LIMITED

发明人： Hirose, Yoshio ,  Yamashita, Koichi ,  Kawahara, Shigeki ,  Sato, Shinji ,  Sasaki, Takeshi ,  Kumagai, Ataru

IPC分类号： H01L27/02 ,  H01L23/52 ,  H01L21/82

CPC分类号： H01L23/528 ,  H01L21/82 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit device includes: a master chip(203) including a basic cell region(201) having a plurality of basic cell arrays(206) arranged thereon, and an input/output cell region(202) having a plurality of input/output cells(207) arranged along the periphery of the basic cell region; a first wiring layer formed on the basic cell region and the input/output cell region via a first insulation layer having contact holes at predetermined positions, the first wiring layer including fixed wirings(LA,508); and a second wiring layer formed on the first wiring layer via a second insulation layer having through holes at predetermined positions, the second wiring layer including programmed wirings(LB,507). Only the wiring pattern of the second wiring layer is suitably changed in accordance with conditions of circuits applied to the input/output cell region and the basic cell region in regions corresponding to the input/output cell region and the basic cell region, thereby greatly reducing a turnaround time of the device.

摘要翻译： 一种半导体集成电路器件，包括：主芯片（203），包括具有布置在其上的多个基本单元阵列（206）的基本单元区域（201），以及具有多个输入/ 输出单元（207），沿着基本单元区域的周边布置; 经由具有在预定位置具有接触孔的第一绝缘层形成在基本单元区域和输入/输出单元区域上的第一布线层，第一布线层包括固定布线（LA，508）; 以及第二布线层，其经由在预定位置具有通孔的第二绝缘层形成在所述第一布线层上，所述第二布线层包括编程布线（LB，507）。 根据与输入/输出单元区域和基本单元区域对应的区域中的输入/输出单元区域和基本单元区域的电路的条件适当地改变第二布线层的布线图案，从而大大降低 设备的周转时间。

公开(公告)号：EP2284712A3

公开(公告)日：2011-06-15

申请号：EP10179486.5

申请日：2000-09-29

申请人： Fujitsu Limited

发明人： Miyake, Hideo ,  Suga, Atsuhiro ,  Nakamura, Yasuki ,  Kamigata, Teruhiko ,  Yoda, Hitoshi ,  Okano, Hiroshi ,  Hirose, Yoshio

IPC分类号： G06F12/12 ,  G06F12/08

CPC分类号： G06F12/0802 ,  G06F2212/2515

摘要： A method of controlling a cache memory that is connected to a main memory with a first address space and capable of acting as a random access memory, which is executed by a computer that accesses the main memory through the cache memory, comprising the steps of: determining whether the cache memory is acting as the random access memory; and assigning a second address space, which is separate from the first address space of the main memory, for the cache memory when the cache memory is acting as the random access memory.

公开(公告)号：EP2284712A2

公开(公告)日：2011-02-16

申请号：EP10179486.5

申请日：2000-09-29

申请人： Fujitsu Limited

发明人： Miyake, Hideo ,  Suga, Atsuhiro ,  Nakamura, Yasuki ,  Kamigata, Teruhiko ,  Yoda, Hitoshi ,  Okano, Hiroshi ,  Hirose, Yoshio

IPC分类号： G06F12/12 ,  G06F12/08

CPC分类号： G06F12/0802 ,  G06F2212/2515

摘要： A method of controlling a cache memory that is connected to a main memory with a first address space and capable of acting as a random access memory, which is executed by a computer that accesses the main memory through the cache memory, comprising the steps of: determining whether the cache memory is acting as the random access memory; and assigning a second address space, which is separate from the first address space of the main memory, for the cache memory when the cache memory is acting as the random access memory.

摘要翻译： 控制高速缓冲存储器的方法也被连接到主存储器与和能够充当随机存取存储器的第一地址空间中，所有这是由计算机执行那样通过高速缓冲存储器访问主存储器，包括以下步骤： 确定性采矿无论高速缓存存储器充当随机存取存储器; 和分配的第二地址空间，所有这些是从主存储器的第一地址空间中，用于高速缓存存储器中。当高速缓冲存储器被用作随机存取存储器是分开的。

公开(公告)号：EP0338817B1

公开(公告)日：1999-09-08

申请号：EP89303912.3

申请日：1989-04-20

申请人： FUJITSU LIMITED

发明人： Hirose, Yoshio ,  Yamashita, Koichi ,  Kawahara, Shigeki ,  Sato, Shinji ,  Sasaki, Takeshi ,  Kumagai, Ataru

IPC分类号： H01L27/02 ,  H01L23/52 ,  H01L21/82

CPC分类号： H01L23/528 ,  H01L21/82 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP0338817A3

公开(公告)日：1992-05-06

申请号：EP89303912.3

申请日：1989-04-20

申请人： FUJITSU LIMITED

发明人： Hirose, Yoshio ,  Yamashita, Koichi ,  Kawahara, Shigeki ,  Sato, Shinji ,  Sasaki, Takeshi ,  Kumagai, Ataru

IPC分类号： H01L27/02 ,  H01L23/52 ,  H01L21/82

CPC分类号： H01L23/528 ,  H01L21/82 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit device includes: a master chip(203) including a basic cell region(201) having a plurality of basic cell arrays(206) arranged thereon, and an input/output cell region(202) having a plurality of input/output cells(207) arranged along the periphery of the basic cell region; a first wiring layer formed on the basic cell region and the input/output cell region via a first insulation layer having contact holes at predetermined positions, the first wiring layer including fixed wirings(LA,508); and a second wiring layer formed on the first wiring layer via a second insulation layer having through holes at predetermined positions, the second wiring layer including programmed wirings(LB,507). Only the wiring pattern of the second wiring layer is suitably changed in accordance with conditions of circuits applied to the input/output cell region and the basic cell region in regions corresponding to the input/output cell region and the basic cell region, thereby greatly reducing a turnaround time of the device.