发明公开
EP0519592A2 Self-aligned planar monolithic integrated circuit vertical transistor process
失效
一种制造自对准的，平面的，单片集成电路用的垂直晶体管的方法。
- 专利标题： Self-aligned planar monolithic integrated circuit vertical transistor process
- 专利标题（中）： 一种制造自对准的，平面的，单片集成电路用的垂直晶体管的方法。
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申请号： EP92303984.6申请日： 1992-05-01
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公开(公告)号： EP0519592A2公开(公告)日： 1992-12-23
- 发明人: Ramde, Amolak R.
- 申请人： NATIONAL SEMICONDUCTOR CORPORATION
- 申请人地址： 2900 Semiconductor Drive P.O. Box 58090 Santa Clara California 95051-8090 US
- 专利权人： NATIONAL SEMICONDUCTOR CORPORATION
- 当前专利权人： NATIONAL SEMICONDUCTOR CORPORATION
- 当前专利权人地址： 2900 Semiconductor Drive P.O. Box 58090 Santa Clara California 95051-8090 US
- 代理机构： Bowles, Sharon Margaret
- 优先权： US716890 19910618
- 主分类号： H01L21/8228
- IPC分类号： H01L21/8228 ; H01L21/761
摘要：
A process for creating self-aligned vertically arrayed planar transistors. The preferred embodiment relates to the simultaneous fabrication of both NPN and PNP planar vertically arrayed transistors in a conventional monolithic, epitaxial, PN junction isolated, integrated circuit. A field oxide is employed to surface isolate the devices and assist in the self-alignment improvement.
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