公开(公告)号：EP2924723B1

公开(公告)日：2023-04-05

申请号：EP15154323.8

申请日：2015-02-09

Inventor： Jonishi, Akihiro

IPC: H01L27/092 ,  H01L21/761 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/423

公开(公告)号：EP3966847A1

公开(公告)日：2022-03-16

申请号：EP19928044.7

申请日：2019-05-04

Applicant: Trieye Ltd.

Inventor： KATZIR, Eran ,  IMMER, Vincent ,  KAPACH, Omer ,  BAKAL, Avraham ,  LEVY, Uriel

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/22 ,  H01L21/74 ,  H01L21/761 ,  H01L29/16 ,  H01L29/167

公开(公告)号：EP2560209B1

公开(公告)日：2020-02-19

申请号：EP12180591.5

申请日：2012-08-16

Applicant: Altera Corporation

Inventor： Watt, Jeffrey T. ,  Rahim, Irfan ,  Xu, Yanzhong ,  Liu, Lin-Shih

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/761

公开(公告)号：EP3501039A1

公开(公告)日：2019-06-26

申请号：EP17765322.7

申请日：2017-08-29

Applicant: Xilinx, Inc.

Inventor： JING, Jing ,  WU, Shuxian ,  SOWARDS, Jane, W.

IPC: H01L21/761 ,  H01L21/8234

Abstract: An example a semiconductor device includes a first circuit and a second circuit formed in a semiconductor substrate. The semiconductor device further includes a first guard structure formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the first guard structure including first discontinuous pairs of n+ and p+ diffusions disposed along a first axis. The semiconductor device further includes a second guard structure formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the second guard structure including second discontinuous pairs of n+ and p+ diffusions disposed along the first axis, the second discontinuous pairs of n+ and p+ diffusions being staggered with respect to the first discontinuous pairs of n+ and p+ diffusions.

公开(公告)号：EP3244200A1

公开(公告)日：2017-11-15

申请号：EP15876971.1

申请日：2015-12-02

Applicant: Hitachi Automotive Systems, Ltd.

Inventor： ONO Kazuo ,  USAGAWA Toshiyuki

IPC: G01N27/00 ,  G01K7/01 ,  H01L21/336 ,  H01L21/761 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L27/088 ,  H01L29/78

CPC classification number: G01N27/4141 ,  G01K7/01 ,  G01N27/00 ,  G01N27/4148 ,  G01R19/10 ,  H01L21/761 ,  H01L21/822 ,  H01L21/8234 ,  H01L23/34 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L27/088 ,  H01L29/78

Abstract: The invention achieves a lower noise of a sense signal of a FET-type hydrogen sensor.
For solving the above problem, one aspect of a sensor system of the invention includes a reference device and a sensor device configured using FETs on a substrate, and further, well potentials of the reference device and the sensor device are electrically isolated from each other.

Abstract translation: 本发明实现了FET型氢传感器的感测信号的较低噪声。 为了解决上述问题，本发明的传感器系统的一个方面包括参考装置和使用基板上的FET配置的传感器装置，并且参考装置和传感器装置的阱电势彼此电隔离。

公开(公告)号：EP3072154A4

公开(公告)日：2017-08-02

申请号：EP13897742

申请日：2013-11-22

Applicant: NXP USA INC

Inventor： BESSE PATRICE ,  LAINE JEAN PHILIPPE ,  ROLLAND ERIC PIERRE

IPC: H01L27/04 ,  H01L21/761 ,  H01L21/762 ,  H01L27/02 ,  H01L29/06 ,  H01L29/45 ,  H01L29/87

CPC classification number: H01L27/0262 ,  H01L21/761 ,  H01L21/76264 ,  H01L27/0259 ,  H01L27/0292 ,  H01L29/0649 ,  H01L29/45 ,  H01L29/87

Abstract: An ESD protection circuit and device structure comprises five transistors, two PNP and three NPN. The five transistors are coupled together so that a first NPN and PNP pair constitute a first silicon controlled rectifier, SCR. The NPN transistor 102 of the first SCR and a third transistor of NPN type are coupled so that they constitute a Darlington pair. A further NPN and PNP pair are coupled together to form a second SCR with the collector of the PNP transistor of the first SCR being coupled with the emitter of the PNP transistor of the second SCR. The circuit is particularly suitable for high voltage triggering applications and two or more devices may be cascaded in series in order to further increase the triggering voltage.

Abstract translation: ESD保护电路和器件结构包括五个晶体管，两个PNP和三个NPN。 五个晶体管耦合在一起，使得第一NPN和PNP对构成第一可控硅SCR。 第一SCR的NPN晶体管102和NPN型的第三晶体管被耦合，从而它们构成达林顿对。 另一个NPN和PNP对耦合在一起以形成第二SCR，其中第一SCR的PNP晶体管的集电极与第二SCR的PNP晶体管的发射极耦合。 该电路特别适用于高压触发应用，并且可以串联两个或更多的器件以进一步增加触发电压。

公开(公告)号：EP3097584A1

公开(公告)日：2016-11-30

申请号：EP15700683.4

申请日：2015-01-16

Applicant: Merus Audio ApS

Inventor： NIELSEN, Allan Nogueras ,  HØYERBY, Mikkel

IPC: H01L21/8238 ,  H01L21/761 ,  H03F3/217

CPC classification number: H01L29/7816 ,  H01L21/761 ,  H01L21/823892 ,  H01L27/0629 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/78 ,  H03F3/2171 ,  H03F3/2173 ,  H03K17/687

Abstract: The present invention relates to an integrated high side gate driver structure for driving a power transistor. The high side gate driver structure comprises a semiconductor substrate comprising a first polarity semiconductor material in which a first well diffusion comprising a second polarity semiconductor material is formed. A peripheral outer wall of the first well diffusion is abutted to the semiconductor substrate. A second well diffusion, comprising first polarity semiconductor material, is arranged inside the first well diffusion such that an outer peripheral wall of the second well diffusion is abutted to an inner peripheral wall of the first well diffusion. The integrated high side gate driver structure further comprises a gate driver comprising a high side positive supply voltage port, a high side negative supply voltage port, a driver input and a driver output, wherein the gate driver comprises a transistor driver arranged in the second well diffusion such that a control terminal of the transistor driver and an output terminal of the transistor driver is coupled to the driver input and the driver output, respectively; the integrated high side gate driver structure also comprises a first electrical connection between the first well diffusion and the high side negative supply voltage port and a second electrical connection between the second well diffusion and the high side negative supply voltage port.

公开(公告)号：EP3038165A1

公开(公告)日：2016-06-29

申请号：EP15201368.6

申请日：2015-12-18

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： DUBOIS, Sébastien ,  ENJALBERT, Nicolas ,  GARANDET, Jean-Paul ,  MARTEL, Benoît ,  VEIRMAN, Jordi

IPC: H01L31/0352 ,  H01L31/068 ,  H01L31/18 ,  H01L21/761 ,  H01L21/04 ,  H01L31/047

CPC classification number: H01L31/0747 ,  H01L21/761 ,  H01L31/0288 ,  H01L31/03529 ,  H01L31/047 ,  H01L31/068 ,  H01L31/1804 ,  H01L31/1864 ,  H01L31/1868 ,  H01L31/202 ,  H01L31/208 ,  Y02E10/547 ,  Y02P70/521

Abstract: La présente invention concerne un procédé de fabrication d'une plaquette (10) d'épaisseur (e), comprenant au moins les étapes consistant en (i) disposer d'un substrat monolithique en silicium dopé p ; (ii) former des défauts cristallographiques sur des parties prédéfinies d'au moins l'une des faces du substrat ; (iii) soumettre le substrat à un recuit thermique ; (iv) mettre en contact tout ou partie de l'une des faces du substrat avec de l'hydrogène ; (v) si nécessaire, favoriser la diffusion de l'hydrogène ; et (vi) soumettre le substrat à un traitement thermique.

Abstract translation: 一种制造厚度晶片的方法，至少包括（i）提供由p掺杂硅制成的单片基板; （ii）在所述基板的至少一个侧面的预定部分中形成晶体缺陷; （iii）使受试者进行热退火; （iv）使基材的一侧的全部或一部分与氢接触; （v）如有必要，促进氢的扩散; 和（vi）对基材进行热处理。

公开(公告)号：EP2965350A1

公开(公告)日：2016-01-13

申请号：EP14713264.1

申请日：2014-03-06

Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： VESCHETTI, Yannick ,  DUBOIS, Sébastien ,  ENJALBERT, Nicolas ,  GARANDET, Jean-Paul ,  VEIRMAN, Jordi

IPC: H01L21/761

CPC classification number: H01L21/761 ,  C30B29/06 ,  C30B33/02 ,  H01L31/03529 ,  H01L31/068 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: The invention relates to a monolithic semi-conductor substrate (10) based on silicon, vertically divided into sub-cells that are isolated from each other, comprising a type-p or type-n silicon base (1) having an interstitial oxygen concentration of between 1017 and 2.1018 cm"3, and including, on at least one of the faces thereof, n+ and/or p+ overdoped boxes that are non-contiguous in relation to each other, characterised in that at least one substrate region, inserted between two successive boxes and extending over the entire thickness of the substrate, is an electrical insulation region (3) having a thermal donor concentration based on interstitial oxygen different from that of the base (1). The invention also relates to methods for producing such a substrate.

Abstract translation: 本发明涉及一种基于硅的整体式半导体衬底（10），其垂直分成彼此分离的子电池，其包含p型或n型硅基（1），其间隙氧浓度为 在1017和2.1018cm 3之间，并且在其至少一个面上包括相对于彼此不连续的n +和/或p +超掺杂盒，其特征在于，至少一个衬底区域插入在两个 连续的盒子并且在衬底的整个厚度上延伸，是具有基于不同于基底（1）的间隙氧的热供体浓度的电绝缘区域（3），本发明还涉及制造这种衬底的方法 。

公开(公告)号：EP2924723A3

公开(公告)日：2015-12-23

申请号：EP15154323.8

申请日：2015-02-09

Applicant: Fuji Electric Co., Ltd.

Inventor： Jonishi, Akihiro

IPC: H01L27/092 ,  H01L29/06 ,  H01L21/761 ,  H01L21/8238 ,  H01L27/06

CPC classification number: H01L27/0635 ,  H01L21/761 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/0623 ,  H01L27/092 ,  H01L28/20 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/405 ,  H01L29/42368 ,  H01L29/735 ,  H01L29/7823

Abstract: An object of the present invention is to provide a semiconductor device that ensures both the optimum conditions of breakdown voltage of the HVIC and current carrying capacity of the pch MOSFET.
In a semiconductor device of the invention, an n - type diffusion region 1 surrounds a high side well region 112 and is electrically isolated from a low side region. In the n - diffusion region 1 formed are a first p type diffusion region 2a and the second p type diffusion region 2b separated with each other. The first p type diffusion region 2a composes a double RESURF structure in an nch MOSFET 105 in the level shift-up circuit 104, and in a high voltage junction terminating structure 111. The second p type diffusion region 2b composes a double RESURF structure of a pch MOSFET 108 of a level shift-down circuit 107. The impurity concentration of the n - type diffusion region 1 is in the range from 1.3 × 10 12 /cm 2 to 2.8 × 10 12 /cm 2 . The impurity concentration of the first p type diffusion region 2a and the impurity concentration of the second p type diffusion region 2b are in the range from 1.1 × 10 12 /cm 2 to 1.4 × 10 12 /cm 2 .

Abstract translation: 本发明的一个目的是提供一种确保HVIC的击穿电压的最佳条件和pch MOSFET的电流承载能力的半导体器件。 在本发明的半导体器件中，n-型扩散区1围绕高侧阱区112并与低侧区电隔离。 在形成的n扩散区1中，形成彼此分离的第一p型扩散区2a和第二p型扩散区2b。 第一p型扩散区2a在电平移位升高电路104中的nch MOSFET 105中以及高电压结终端结构111中构成双RESURF结构。第二p型扩散区2b构成一个双RESURF结构的a 电平移位电路107的pch MOSFET 108.n型扩散区1的杂质浓度在1.3×10 12 / cm 2至2.8×10 12 / cm 2的范围内。 第一p型扩散区域2a的杂质浓度和第二p型扩散区域2b的杂质浓度在1.1×1012 / cm2至1.4×1012 / cm2的范围内。